This article presents a 3 THz CMOS image sensor (Tera-CIS). The sensor has a column-parallel readout (CPRO) architecture that integrates an antenna-coupled pixel array and CPRO circuit chains on a monolithic chip. The proposed compact two-transistor (2T) pixel adopts a step-covered patch antenna and a defected ground structure (DGS) to obtain sufficient sensitivity and bandwidth. The step-covered patch antenna model is developed to predict pixel performances precisely. The DGS structure suppresses mutual coupling among adjacent pixels and shrinks the pixel pitch. In the CPRO circuit chain, chopping and oversampling techniques are employed to reduce noise and flexibly balance the dynamic range (DR) characteristics with the imaging rate. A digital decimation filter (DDF) with a time-multiplexing fashion is adopted to alleviate resource pressure. A 16.4k-pixel Tera-CIS was fabricated with a standard $0.18~\mu \text{m}$ CMOS process. A 3 THz imaging platform with four different continuous-wave (CW) terahertz quantum cascade lasers was established. The pixel sensitivity was 753 V/W at 3.4 THz, with a measured detection bandwidth of 0.78 THz (from 3.08 to 3.86 THz). The DR in the voltage domain of the sensor reached 73 dB at 8 fps while the maximum DR in the power domain was 39.8 dB. Meanwhile, the sensor can operate up to 130 fps. The imaging system can achieve high-resolution imaging and clearly identify concealed objects.

中文翻译：

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3 THz CMOS 图像传感器


本文介绍了一种 3 THz CMOS 图像传感器 (Tera-CIS)。该传感器采用列并行读出 (CPRO) 架构，在单片芯片上集成了天线耦合像素阵列和 CPRO 电路链。所提出的紧凑型双晶体管（2T）像素采用阶梯覆盖贴片天线和缺陷接地结构（DGS）以获得足够的灵敏度和带宽。开发阶梯覆盖贴片天线模型是为了精确预测像素性能。 DGS结构抑制了相邻像素之间的相互耦合并缩小了像素间距。在CPRO电路链中，采用斩波和过采样技术来降低噪声并灵活平衡动态范围（DR）特性与成像速率。采用时分复用方式的数字抽取滤波器（DDF）来缓解资源压力。 16400 像素 Tera-CIS 采用标准制造$0.18~\mu \text{m}$ CMOS工艺。建立了具有四种不同的连续波（CW）太赫兹量子级联激光器的3 THz成像平台。 3.4 THz 时像素灵敏度为 753 V/W，测得的检测带宽为 0.78 THz（从 3.08 到 3.86 THz）。传感器电压域的 DR 在 8 fps 时达到 73 dB，而功率域的最大 DR 为 39.8 dB。同时，传感器的运行速度可达 130 fps。该成像系统可实现高分辨率成像，清晰识别隐藏物体。