The proposed single-ended transmitter for memory interfaces is an impedance-matched transmitter that utilizes a single ring-oscillator-based time-domain ZQ calibration. This ZQ calibration technique eliminates the offsets by using a gain-controlled ring oscillator with late-case forcing, resulting in low maximum/average error rates. The transmitter incorporates a phase equalization method to compensate for pre-cursor inter-symbol interference (ISI) without affecting the impedance matching achieved by ZQ calibration. This phase equalization is implemented by minimizing hardware to overcome the design complexity of conventional phase equalization and reduce power consumption. The prototype chip is fabricated in the 65-nm CMOS process. The transmitter and the ZQ calibration scheme occupy an area of 0.074 and 0.041 mm2, respectively. The proposed ZQ calibration achieves a maximum error rate of 1.5% and an average error rate of 0.7%. In addition, the transmitter achieves an energy efficiency of 1.145 pJ/bit and an FoM of 0.11 pJ/bit/(dB/pin) at 12 Gb/s.

中文翻译：

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具有用于存储器接口的基于单环形振荡器的时域 ZQ 校准的单端阻抗匹配发送器


所提出的用于存储器接口的单端发射器是一种阻抗匹配发射器，它利用基于单环形振荡器的时域 ZQ 校准。这种 ZQ 校准技术通过使用具有后期情况强制的增益控制环形振荡器来消除偏移，从而降低最大/平均错误率。该发射机采用相位均衡方法来补偿前体符号间干扰 (ISI)，而不影响通过 ZQ 校准实现的阻抗匹配。这种相位均衡是通过最小化硬件来实现的，以克服传统相位均衡的设计复杂性并降低功耗。原型芯片采用 65 nm CMOS 工艺制造。发射机和 ZQ 校准方案分别占用 0.074 和 0.041 mm2 的面积。所提出的 ZQ 校准实现了 1.5% 的最大错误率和 0.7% 的平均错误率。此外，发射器在 12 Gb/s 速率下实现了 1.145 pJ/bit 的能效和 0.11 pJ/bit/(dB/pin) 的 FoM。