Since combinatorial optimization problems (COPs) are a class of non-deterministic polynomial-time (NP)-hard problems, it is impracticable to solve them in brute-force searches, which results in high energy consumption and long computation latency. The annealing processors based on the Ising model are naturally oriented to find approximate solutions. However, these processors face the challenges of frequent data movement between computing elements and memory units, resulting in significantly large area and high energy consumption. To address these issues, we present a fully digital annealing processor based on compute-in-memory (CIM) architecture. To enhance area efficiency, a CIM coefficient array is designed with an interaction coefficient reuse strategy. Moreover, a sparsity-aware adder tree is proposed to reduce unnecessary add operations, which can improve the energy efficiency. For searching the lowest energy state of the Ising model, a nonlinear probability flipping (NPF) approximate circuit is designed, which is based on a voting mechanism and on-chip random number generation with low hardware overhead. The proposed annealing processor is fabricated in a 55-nm CMOS process and used to solve the max-cut problem as well as the image segmentation problem. The measured results confirm the high energy efficiency (2.4 fJ at 0.9 V per spin) and the high area efficiency (402 μm2\mu\text{m}^2 per spin).

中文翻译：

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一种具有交互系数重用和稀疏能量计算的内存计算退火处理器，用于解决组合优化问题


由于组合优化问题（COP）是一类非确定性多项式时间（NP）难题，通过强力搜索来解决它们是不切实际的，这会导致高能耗和长计算延迟。基于伊辛模型的退火处理器自然地面向寻找近似解。然而，这些处理器面临着计算元件和存储单元之间频繁的数据移动的挑战，导致面积极大且能耗高。为了解决这些问题，我们提出了一种基于内存计算 (CIM) 架构的全数字退火处理器。为了提高面积效率，CIM系数数组设计了交互系数重用策略。此外，提出了一种稀疏感知加法器树来减少不必要的加法操作，从而提高能源效率。为了搜索伊辛模型的最低能量态，设计了一种非线性概率翻转（NPF）近似电路，该电路基于投票机制和片上随机数生成，硬件开销较低。所提出的退火处理器采用 55 nm CMOS 工艺制造，用于解决最大切割问题以及图像分割问题。测量结果证实了高能量效率（每次旋转 0.9 V 时为 2.4 fJ）和高面积效率（每次旋转 402 μm2\mu\text{m}^2）。