Level-crossing ADCs (LCADCs) operate on changes in the input signal, resulting in an event-driven power consumption and data output. For signals with time-sparse activity (e.g., neural action potentials, and ECG), such ADCs can offer advantages at the system level through the reduced data rate that decreases the transmission and/or processing power, making them well-suited for low-power edge applications. Current implementations are, however, limited in performance and power efficiency. Due to the asynchronous output stream, it is also difficult to interface such LCADCs with (conventional) clocked digital processing circuits/transmitters. This article introduces a new LCADC topology, with clocked comparators but with an adaptive clocking scheme. It has a low power consumption and can seamlessly be integrated with any type of processing/transmission circuit. This article first analyzes the major bottleneck to the power consumption of the classical continuous-time (CT) LCADCs. A new, more power-efficient topology with clocked comparators is then introduced. Thanks to the adaptive clocking algorithm, the power consumption scales with the signal activity. The discrete-time (DT) topology can achieve a 10 ×\times –100 ×\times lower comparator power depending on the signal activity. A prototype IC with an 8-bit 15-kHz BW LCADC is implemented in a 40-nm CMOS technology. Measurement results show that the ADC has an activity-based power consumption from 0.92 μ\mu W for an ECG signal to 5.38 μ\mu W for a 15-kHz full-scale sine wave. The ADC has 10.4 ENOB and reaches a peak Walden FOM of 138 fJ/conv. For an ECG signal as input, the ADC can achieve a 30% reduction in data and a 3 ×\times reduction in ADC I/O power. This showcases how such LCADCs can yield significant benefits in edge systems.

中文翻译：

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针对时间稀疏边缘应用的具有自适应时钟的 10.4-ENOB 0.92´5.38-$\mu$W 事件驱动电平交叉 ADC 的分析和设计


电平交叉 ADC (LADC) 根据输入信号的变化进行操作，从而产生事件驱动的功耗和数据输出。对于具有时间稀疏活动的信号（例如，神经动作电位和心电图），此类 ADC 可以通过降低数据速率来提供系统级优势，从而降低传输和/或处理能力，使它们非常适合低功耗电源边缘应用。然而，当前的实现在性能和功率效率方面受到限制。由于异步输出流，也很难将此类 LADC 与（传统）时钟数字处理电路/发射器连接。本文介绍了一种新的 LADC 拓扑，具有时钟比较器，但具有自适应时钟方案。它功耗低，可以与任何类型的处理/传输电路无缝集成。本文首先分析了经典连续时间（CT）LADC 功耗的主要瓶颈。然后引入了一种具有时钟比较器的新的、更节能的拓扑。得益于自适应时钟算法，功耗随信号活动而变化。根据信号活动，离散时间 (DT) 拓扑可以实现 10 ×\times –100 ×\times 的较低比较器功耗。具有 8 位 15kHz BW LADC 的原型 IC 采用 40 nm CMOS 技术实现。测量结果表明，ADC 的基于活动的功耗从 ECG 信号的 0.92 μμW 到 15 kHz 满量程正弦波的 5.38 μμW 不等。 ADC 具有 10.4 ENOB，并达到 138 fJ/conv 的峰值 Walden FOM。对于 ECG 信号作为输入，ADC 可以实现数据量减少 30% 以及 ADC I/O 功耗减少 3 倍。 这展示了此类 LADC 如何在边缘系统中产生显着优势。