This article presents a frequency synthesizer for generating quadrature local-oscillator (LO) waveforms covering an octave range of 6 to 12-GHz. It uses two voltage-controlled oscillators (VCO) to cover an octave range from 12 to 24 GHz. The VCOs employ inductor mode switching in addition to conventional capacitor switching to obtain a wide tuning range while maintaining a good phase noise figure of merit (FoM). Modulus-dependent delay (MDD) of the feedback divider increases jitter in fractional- NN mode. The delay change can exceed 100 ps when the number of stages in the divider chain changes. A new digital technique, which can be realized with minor modifications to the conventional digital delta-sigma modulator (DDSM), is implemented to overcome this effect. The delay change is turned into a periodic error at half the reference frequency that is then filtered by the loop filter. The prototype synthesizer in 65-nm CMOS occupies 0.54 mm2\text{mm}^\text{2} and consumes 66 mW at the highest frequency from a 1-V supply, including buffers and dividers. The nominal loop bandwidth is 280 kHz. The integrated jitter is dominated by the VCOs and is 400, 300, and 500 fs in the 6 to 8-GHz, 8 to 10-GHz, and 10 to 12-GHz ranges, respectively. The worst case reference spurs are below −60\mathbf{-60} dBc and the fractional spurs are below −31\mathbf{-31} dBc.

中文翻译：

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6 至 12 GHz 小数 $N$ 频率合成器，采用数字技术来应对模数相关的反馈分频器延迟


本文介绍了一种频率合成器，用于生成覆盖 6 至 12 GHz 倍频程范围的正交本振 (LO) 波形。它使用两个压控振荡器 (VCO) 来覆盖 12 至 24 GHz 的倍频程范围。除了传统的电容器开关之外，VCO 还采用电感器模式开关来获得宽调谐范围，同时保持良好的相位噪声品质因数 (FoM)。反馈分频器的模数相关延迟 (MDD) 会增加小数 NN 模式中的抖动。当分频器链中的级数发生变化时，延迟变化可能会超过 100 ps。采用一种新的数字技术来克服这种影响，该技术只需对传统数字 Delta-Sigma 调制器 (DDSM) 进行少量修改即可实现。延迟变化转化为参考频率一半的周期误差，然后由环路滤波器进行滤波。 65 nm CMOS 原型合成器占用 0.54 mm2\text{mm}^\text{2}，在 1V 电源（包括缓冲器和分频器）的最高频率下功耗为 66 mW。标称环路带宽为 280 kHz。集成抖动主要由 VCO 控制，在 6 至 8 GHz、8 至 10 GHz 和 10 至 12 GHz 范围内分别为 400、300 和 500 fs。最坏情况下的参考杂散低于 -60\mathbf{-60} dBc，分数杂散低于 -31\mathbf{-31} dBc。