This article presents a dynamic range (DR) enhanced discrete-time delta–sigma modulator (DTDSM) applied to the Internet of Things (IoT). It is based on an asynchronous 1.5-bit successive-approximation-resister (SAR) quantizer and a tri-level feedback capacitive digital-to-analog converter (CDAC), eliminating the dynamic element matching (DEM) overhead. The proposed DR enhancement (DRE) technique based on a variable threshold ( VTHV_{\text{TH}} ) allows the system to achieve maximum benefits at different input amplitudes. The system is configured in a high loop gain mode at small input amplitudes, providing the system with a stronger noise-shaping (NS) capability. The system is configured in the maximum stable amplitude (MSA) mode for large input amplitudes. In addition, we modified the working model of the cascoded floating inverter amplifier (FIA) in the weak inversion region. The prototype DTDSM is implemented in a 180-nm CMOS process, achieving a 94.7-dB DR and 92.4-dB signal-to-noise-and-distortion ratio (SNDR) at a 700-Hz bandwidth with only 2.3- μ\mu W power consumption. As a result, the Schreier figure-of-merit (FoM) for SNDR and DR is 177.2 and 179.5 dB, respectively.

中文翻译：

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具有动态范围增强和三级 CDAC 的节能离散时间 Delta igma 调制器


本文介绍了一种应用于物联网 (IoT) 的动态范围 (DR) 增强型离散时间 Delta-Sigma 调制器 (DTDSM)。它基于异步 1.5 位逐次逼近电阻 (SAR) 量化器和三级反馈电容数模转换器 (CDAC)，消除了动态元件匹配 (DEM) 开销。所提出的基于可变阈值（ VTHV_{\text{TH}} ）的 DR 增强（DRE）技术允许系统在不同输入幅度下实现最大效益。该系统在小输入幅度下配置为高环路增益模式，为系统提供更强的噪声整形（NS）能力。系统配置为最大稳定振幅 (MSA) 模式，以实现大输入振幅。此外，我们修改了级联浮动反相放大器（FIA）在弱反相区的工作模型。原型 DTDSM 采用 180 nm CMOS 工艺实现，在 700 Hz 带宽下实现 94.7 dB DR 和 92.4 dB 信噪比和失真比 (SNDR)，仅需 2.3 μ\mu W功耗。因此，SNDR 和 DR 的 Schreier 品质因数 (FoM) 分别为 177.2 和 179.5 dB。