This article presents a 0.68-THz receiver with the third-order subharmonic mixing in a 65-nm CMOS technology. In this work, a third-order subharmonic mixer based on a double-balanced topology is proposed. The spurious mixing product of the mixer is utilized to increase the IF output of the mixer, thus improving the conversion gain and noise figure of the mixer. Besides, compensating capacitors are incorporated in the double-balanced topology to alleviate the severe signal imbalance in this topology at very high frequencies caused by its layout asymmetry. With enhanced signal balance, the conversion gain, noise figure, and isolation of the third-order subharmonic mixer are improved. The receiver achieves a measured noise figure of 28.4 dB at 682 GHz, including the loss of the antenna. Among all the silicon receivers above 430 GHz, this work has the lowest noise figure. Because of the inherent wide bandwidth of the double-balanced topology, the high order of the subharmonic mixer, and the high multiplying factor of the local oscillator (LO) generation circuits, the proposed receiver with an integrated voltage-controlled oscillator obtains a measured input frequency range of 138 GHz, which is the highest among all the silicon receivers above 400 GHz.

中文翻译：

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采用 65 nm CMOS 封装的具有三阶分谐波混频的 0.68-THz 接收器


本文介绍了一种采用 65 nm CMOS 技术并具有三阶分谐波混频的 0.68-THz 接收器。在这项工作中，提出了一种基于双平衡拓扑的三阶分谐波混频器。利用混频器的杂散混频积来增大混频器的中频输出，从而提高混频器的变频增益和噪声系数。此外，双平衡拓扑中还加入了补偿电容器，以缓解该拓扑在极高频率下由于布局不对称而导致的严重信号不平衡。通过增强的信号平衡，三阶分谐波混频器的转换增益、噪声系数和隔离度均得到改善。接收器在 682 GHz 下测得的噪声系数为 28.4 dB，其中包括天线损耗。在所有 430 GHz 以上的硅接收器中，该作品的噪声系数最低。由于双平衡拓扑固有的宽带宽、分谐波混频器的高阶以及本地振荡器（LO）生成电路的高倍增系数，所提出的具有集成压控振荡器的接收器获得测量输入频率范围为138 GHz，是所有400 GHz以上硅接收器中最高的。