This article presents a 3.3–4.5-GHz fractional- NN analog sampling phase-locked loop (SPLL). A merged constant-slope digital-to-time converter and sampling phase detector (CSDTC-SPD) allows phase error detection as well as quantization noise (QN) cancellation in a single ramp generation, which reduces the source of noise and nonlinearity. A modified multimodulus divider (MMDIV) with two phase retimers reduces the required CSDTC-SPD linear range and decreases the noise from the CSDTC-SPD. To verify the principle, a prototype SPLL was implemented and fabricated in a conventional 40-nm CMOS technology. The measured results show the merits of an rms jitter of 203 fs with 2.4-mW power, which leads to a phase-locked loop (PLL) figure of merit (FoM) of −250 dB.

中文翻译：

---

具有合并的恒定斜率 DTC 和采样 PD 的小数 N 采样 PLL


本文介绍了一种 3.3–4.5 GHz 小数 NN 模拟采样锁相环 (SPLL)。合并的恒定斜率数字时间转换器和采样相位检测器 (CSDTC-SPD) 允许在单个斜坡生成中进行相位误差检测和量化噪声 (QN) 消除，从而减少噪声和非线性源。带有两相重定时器的改进型多模分频器 (MMDIV) 降低了所需的 CSDTC-SPD 线性范围，并降低了 CSDTC-SPD 的噪声。为了验证原理，采用传统的 40 nm CMOS 技术实现并制造了原型 SPLL。测量结果显示了 2.4 mW 功率下 203 fs 的均方根抖动的优点，这导致锁相环 (PLL) 品质因数 (FoM) 为 -250 dB。