This article presents a 116-Gb/s PAM4 voltage-mode (VM) transmitter (TX). The TX includes a 4:1-multiplexed 7-bit digital-to-analog converter (DAC) driver with an eight-tap feedforward equalizer (FFE). A high energy efficiency of 0.9 pJ/bit was achieved by novel data and clock path architectures that operate at up to 14.5 GHz. In the data path, the serializer is based mainly on MUXes that are biased in an unregulated low voltage supply of 0.75 V. Since high-quality clocks are not needed in the data path, the buffer loading of the clocks can be reduced. In the clock path, 1-unit interval (UI) pulse generation is formed to sample the data inside the 4:1 multiplexer (MUX) driver. It is shown that the driver is compatible to IEEE802.3-ck and OIF CEI-112G-LR PAM4 standards. The TX was fabricated in a TSMC 5-nm FinFET node and occupies an area of 0.082 mm2 ( 300×272μm300 \times 272\,\,\mu \text{m} ).

中文翻译：

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采用 5 nm FinFET 封装、具有八抽头 FFE 的 116 Gb/s PAM4 0.9 pJ/b 发送器


本文介绍了一款 116 Gb/s PAM4 电压模式 (VM) 发送器 (TX)。 TX 包括一个 4:1 复用 7 位数模转换器 (DAC) 驱动器和一个八抽头前馈均衡器 (FFE)。通过运行频率高达 14.5 GHz 的新颖数据和时钟路径架构实现了 0.9 pJ/bit 的高能效。在数据路径中，串行器主要基于在 0.75V 的未调节低压电源下偏置的 MUX。由于数据路径中不需要高质量时钟，因此可以减少时钟的缓冲器负载。在时钟路径中，形成 1 单位间隔 (UI) 脉冲生成，以对 4:1 多路复用器 (MUX) 驱动器内的数据进行采样。结果表明，该驱动程序兼容IEEE802.3-ck和OIF CEI-112G-LR PAM4标准。 TX 采用 TSMC 5 nm FinFET 节点制造，占用面积 0.082 mm2 ( 300×272μm300 \times 272\,\,\mu \text{m} )。