This article presents Scaling-computing-in-memory (CIM), an energy-efficient embedded dynamic random access memory (eDRAM)-based in-memory-computing (IMC) accelerator with a dynamic-scaling readout for signal-to-quantization-noise ratio (SQNR) boosting and analog-to-digital converter (ADC) overhead reduction. It greatly saves the ADC cost by reducing the required number of ADC-bit and ADC operations by codesigning the algorithm and hardware. Scaling-CIM proposes three key features: 1) dynamic scaling ADC (DSA) boosts SQNR of multibit operation even with low-bit ADC; 2) adaptive analog bit-parallel (AABP) accumulation reduces the redundant ADC operation; and 3) layer-wise adaptive bit-truncation (LABT) search further enhances efficiency on benchmarks. The Scaling-CIM is fabricated in 28-nm CMOS technology and occupies a 2.03-mm2 die area with an 800-kb eDRAM cell. It achieves 39.7-TOPS/W (8–9 b) energy efficiency on the RestNet-18 benchmark and 1.96×1.96\times higher efficiency figure of merit (FoM) than the previous IMC-based accelerator.

中文翻译：

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Scaling-CIM：具有动态扩展 ADC 和自适应模拟操作的 eDRAM 内存计算加速器


本文介绍了内存扩展计算 (CIM)，这是一种基于节能嵌入式动态随机存取存储器 (eDRAM) 的内存计算 (IMC) 加速器，具有用于信号到量化的动态扩展读出功能。噪声比 (SQNR) 提升和模数转换器 (ADC) 开销降低。它通过对算法和硬件进行联合设计来减少所需的 ADC 位和 ADC 操作数量，从而大大节省了 ADC 成本。 Scaling-CIM 提出了三个关键特性：1) 动态缩放 ADC (DSA) 提高了多位操作的 SQNR，即使使用低位 ADC 也是如此； 2) 自适应模拟位并行（AABP）累加减少了冗余的ADC操作； 3）分层自适应位截断（LABT）搜索进一步提高了基准测试的效率。 Scaling-CIM 采用 28 nm CMOS 技术制造，占用 2.03 mm2 芯片面积和 800 kb eDRAM 单元。它在 RestNet-18 基准上实现了 39.7-TOPS/W (8–9 b) 的能效，并且比之前基于 IMC 的加速器高出 1.96×1.96 倍的效率品质因数 (FoM)。