<br>一种基于低死区时间 FPGA 的时间数字转换器，采用资源高效的下采样复用编码和双直方图，适用于 LiDAR 应用,IEEE Transactions on Industrial Electronics

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一种基于低死区时间 FPGA 的时间数字转换器，采用资源高效的下采样复用编码和双直方图，适用于 LiDAR 应用
IEEE Transactions on Industrial Electronics ( IF 7.5 ) Pub Date : 2024-01-12 , DOI: 10.1109/tie.2023.3347843
Shaoxian Liu ₁ , Yanxian Zhou ₁ , Shaolin Liao ₁ , Xianbo Li ₁

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本文介绍了一种低死区时间分辨率可调时间数字转换器 (TDC)，采用资源高效的下采样复用 (DS-MUX) 编码和基于现场可编程门阵列 (FPGA) 的双直方图。通过采用所提出的 DS-MUX 编码，可以在一个时钟周期内同时处理延迟线中由不同回声事件触发的多个转换沿，这优于传统的温度计到二进制编码器。通过采用所提出的基于块随机存取存储器（BRAM）的具有独特地址重新映射的双直方图模块，直方图吞吐量得到提高，同时借助粗略累加器删除无效时间戳。此外，还应用箱抽取和箱宽度校准来增强线性度和精度。所提出的 TDC 在 28 nm FPGA 上实现，将死区时间减少至 0.59 倍时钟周期，从而将转换率提高 1.7 倍。更重要的是，所提出的 TDC 仅消耗 402 个查找表、588 个触发器和 2.5 个 BRAM。据我们所知，这是第一个基于 FPGA 的资源高效型 TDC，通过基于 BRAM 的直方图将死区时间减少到一个时钟周期以下，适用于多通道光检测和测距应用。

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A Low-Dead-Time FPGA-Based Time-to-Digital Converter Employing Resource-Efficient Downsampling-Multiplexing Encoding and Dual-Histogramming for LiDAR Applications

This article presents a low-dead-time resolution-adjustable time-to-digital converter (TDC) employing resource-efficient downsampling-multiplexing (DS- MUX) encoding and dual-histogramming based on field-programmable gate array (FPGA). By adopting the proposed DS-MUX encoding, multiple transition edges in the delay line that are triggered by different echo events can be processed simultaneously within one clock cycle, which excels traditional thermometer-to-binary encoders. By employing the proposed block random-access memory (BRAM) based dual-histogramming module with unique address remapping, the histogramming throughput is improved while invalid timestamps are removed with the help of a coarse accumulator. In addition, bin decimation and bin-width calibration are applied to enhance linearity and precision. Implemented on a 28-nm FPGA, the proposed TDC reduces the dead time to 0.59x clock cycle and thus improves the conversion rate by 1.7x. More importantly, the proposed TDC only consumes 402 look-up tables, 588 flip-flops and 2.5 BRAMs. To the best of our knowledge, this is the first resource-efficient FPGA-based TDC that reduces dead time to below one clock cycle with BRAM-based histogramming for multichannel light detection and ranging applications.

更新日期：2024-01-12

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