In the wake of dwindling Moore’s Law, to address the rapidly increasing complexity and cost of fabricating large-scale, monolithic systems-on-chip (SoCs), the industry has adopted dis-aggregation as a solution, wherein a large monolithic SoC is partitioned into multiple smaller chiplets that are then assembled into a large system-in-package (SiP) using advanced packaging substrates such as silicon interposer. For such interposer-based SiPs, there is a push to realize on-interposer inter-chiplet communication bandwidth of multi-Tb/s and end-to-end communication latency of no more than 10 ns. This push comes as the natural progression from some recent prior works on SiP design, and is driven by the proliferating bandwidth demand of modern data-intensive workloads. To meet this bandwidth and latency goal, prior works have focused on a potential solution of using the silicon photonic interposer (SiPhI) for integrating and interconnecting a large number of chiplets into an SiP. Despite the early promise, the existing designs of on-SiPhI interconnects still have to evolve by leaps and bounds to meet the goal of multi-Tb/s bandwidth. However, the possible design pathways, upon which such an evolution can be achieved, have not been explored in any prior works yet. In this paper, we have identified several design pathways that can help evolve on-SiPhI interconnects to achieve multi-Tb/s aggregate bandwidth. We perform an extensive link-level and system-level analysis in which we explore these design pathways in isolation and in different combinations of each other. From our link-level analysis, we have observed that the design pathways that simultaneously enhance the spectral range and optical power budget available for wavelength multiplexing can render aggregate bandwidth of up to 4 Tb/s per on-SiPhI link. We also show that such high-bandwidth on-SiPhI links can substantially improve the performance and energy-efficiency of the state-of-the-art CPU and GPU chiplets based SiPs.

随着摩尔定律的逐渐衰弱，为了解决制造大规模单片系统芯片 (SoC) 的复杂性和成本迅速增加的问题，业界采用了分解作为解决方案，其中将大型单片 SoC 进行分区分成多个较小的小芯片，然后使用硅中介层等先进封装基板组装成大型系统级封装 (SiP)。对于此类基于内插器的 SiP，需要实现多 Tb/s 的内插器小芯片间通信带宽和不超过 10 ns 的端到端通信延迟。这一推动是近期 SiP 设计方面的一些工作的自然进展，并且受到现代数据密集型工作负载不断增长的带宽需求的推动。为了满足这一带宽和延迟目标，之前的工作重点关注使用硅光子中介层 (SiPhI) 将大量小芯片集成和互连到 SiP 中的潜在解决方案。尽管有早期的承诺，SiPhI 互连的现有设计仍然需要飞速发展才能满足多 Tb/s 带宽的目标。然而，之前的任何工作尚未探索实现这种演变的可能设计途径。在本文中，我们确定了几种有助于发展 SiPhI 互连以实现多 Tb/s 聚合带宽的设计途径。我们进行了广泛的链路级和系统级分析，其中我们单独探索这些设计路径以及彼此不同的组合。从我们的链路级分析中，我们观察到，同时增强可用于波长复用的光谱范围和光功率预算的设计路径可以使每个 SiPhI 链路的总带宽高达 4 Tb/s。我们还表明，这种高带宽 SiPhI 链路可以显着提高基于 SiP 的最先进 CPU 和 GPU 小芯片的性能和能效。