55 μ55~\mu m depth TSV-to-pad Cu/SiO2 hybrid bonding for the integration of Si interposer and DRAM has been demonstrated by room temperature bonding and an annealing process. Optimization of surface pretreatment is the key to bonding of Cu and SiO2 with high quality at the same time. In addition, the TSV protrusion issue, which would cause failure of multiple layer stacking, was effectively improved by Cu grain stabilization process and pre-treatment adjustment. The electrical measurements were performed, showing the low and stable TSV resistance. Thus, the TSV-to-pad hybrid bonding with no μ\mu -bumps is promising for further scaling and stacking in HBM or chiplet integration scenarios.

中文翻译：

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TSV 集成与芯片级 TSV 到焊盘 Cu/SiO钪混合键合，用于 DRAM 多层堆叠


用于集成硅中介层和 DRAM 的 55 μ55~μ m 深度 TSV 到焊盘 Cu/SiO2 混合键合已通过室温键合和退火工艺得到验证。表面预处理的优化是Cu和SiO2同时高质量结合的关键。此外，通过Cu晶粒稳定工艺和前处理调整，有效改善了导致多层堆叠失败的TSV突出问题。进行了电气测量，结果显示 TSV 电阻低且稳​​定。因此，没有 μ\mu 凸块的 TSV 到焊盘混合键合有望在 HBM 或小芯片集成场景中进一步缩放和堆叠。