A decoupled inverter pair sense amplifier (DIPSA) is proposed for improved sensing in differential SRAM. The DIPSA is designed at 45-nm technology node with a decreased sensing delay of 31.44% and 28.44% over the conventional latch-type sense amplifier (CLSA) and current-latched SA with an NMOS footswitch (CSANF) at 1.1 V, respectively. The performance of DIPSA is validated using delay and power consumption comparison with prior SA designs across a set of supply voltages. Monte Carlo simulation for 3\(\sigma \) deviation yields a reliable design with no read failures and mean delay of 488.81 ps across the 1k data points with a deviation of 54.87 ps. The threshold voltage variation contribution to process variation is considered for these calculations. The sizing of the decoupling transistors is discussed and its impact on the delay and power of DIPSA shown. The performance of existing voltage and current sense amplifiers is compared to DIPSA.

提出了一种解耦反相器对读出放大器 (DIPSA)，以改进差分 SRAM 中的读出。DIPSA 采用 45 nm 技术节点设计，与传统锁存型感应放大器 (CLSA) 和具有 NMOS 脚踏开关 (CSANF) 的电流锁存 SA (CSANF) 在 1.1 V 下的感应延迟分别降低了 31.44% 和 28.44%。通过在一组电源电压下与之前的 SA 设计进行延迟和功耗比较，可以验证 DIPSA 的性能。蒙特卡罗模拟 3 \(\sigma \)偏差产生了可靠的设计，没有读取失败，1k 数据点的平均延迟为 488.81 ps，偏差为 54.87 ps。这些计算考虑了阈值电压变化对过程变化的贡献。讨论了去耦晶体管的尺寸，并显示了它对 DIPSA 延迟和功率的影响。现有电压和电流检测放大器的性能与 DIPSA 进行了比较。