The practical application of two-dimensional (2D) semiconductors for high-performance electronics requires the integration with large-scale and high-quality dielectrics—which however have been challenging to deposit to date, owing to their dangling-bonds-free surface. Here, we report a dry dielectric integration strategy that enables the transfer of wafer-scale and high-κ dielectrics on top of 2D semiconductors. By utilizing an ultra-thin buffer layer, sub-3 nm thin Al₂O₃ or HfO₂ dielectrics could be pre-deposited and then mechanically dry-transferred on top of MoS₂ monolayers. The transferred ultra-thin dielectric film could retain wafer-scale flatness and uniformity without any cracks, demonstrating a capacitance up to 2.8 μF/cm², equivalent oxide thickness down to 1.2 nm, and leakage currents of ~10⁻⁷A/cm². The fabricated top-gate MoS₂ transistors showed intrinsic properties without doping effects, exhibiting on-off ratios of ~10⁷, subthreshold swing down to 68 mV/dec, and lowest interface states of 7.6×10⁹cm⁻² eV⁻¹. We also show that the scalable top-gate arrays can be used to construct functional logic gates. Our study provides a feasible route towards the vdW integration of high-κ dielectric films using an industry-compatible ALD process with well-controlled thickness, uniformity and scalability.

二维 (2D) 半导体在高性能电子产品中的实际应用需要与大规模和高质量的电介质集成——然而，由于其无悬键表面，迄今为止沉积一直具有挑战性。在这里，我们报告了一种干电介质集成策略，该策略可以在 2D 半导体顶部转移晶圆级和高 κ 电介质。通过利用超薄缓冲层，亚 3 nm 薄的 Al ₂ O ₃或 HfO _{2电介质可以预先沉积，然后机械干法转移到 MoS 2}单层的顶部。转移的超薄介电薄膜可以保持晶圆级的平整度和均匀性，没有任何裂纹，电容高达 2.8 μF/cm^{如图 2 所示}，等效氧化物厚度降至 1.2 nm，漏电流约为 10 ^-7 A/cm ²。制造的顶栅 MoS _{2晶体管表现出无掺杂效应的固有特性，表现出~10} ⁷的开关比、低至 68 mV/dec 的亚阈值摆幅和 7.6×10 9 ^cm -2 ^eV -1^的最低界面态。我们还展示了可扩展的顶门阵列可用于构建功能逻辑门。我们的研究为使用工业兼容的 ALD 工艺实现高 κ 介电薄膜的 vdW 集成提供了一条可行的途径，该工艺具有良好控制的厚度、均匀性和可扩展性。