This paper contains an in-depth investigation into a modularized and parameterized AES implementation with options for the addition of many different AES optimizations. This implementation takes advantage of the low complexity and high malleability of the AES standard’s hardware implementation and its ability to integrate with different block modes of operation. Through investigation of the various available optimizations and implementation methodologies, a high frequency, low power, and low area AES implementation is presented. Results are delivered in an SoC 90nm technology using a combination of multiple industry-standard tools. Results compare the different optimizations and Power, Performance, and Area (PPA) compromises available to AES hardware as well as different options for implementation configuration. This work also presents a new design optimization for AES that provides a significant decrease in the critical path of the hardware design of the operation. In addition to this, this work presents a pipelined architecture which utilizes the optimized AES core to obtain a high throughput.