Untrusted third parties and untrustworthy foundries highlighted the significance of hardware security in the present-day world. Because of the globalization of integrated circuit (IC) design flow in the semiconductor industry, hardware security issues must be taken to prevent intellectual property (IP) piracy. Logic encryption is an efficient method to protect circuits from IP piracy, reverse engineering, and malicious tampering of IC for Trojan insertion. Researchers have proposed many logic encryption methods, which lead to overhead in circuit design parameters such as area, power, and performance. This paper aims to bring a trade-off between these parameters, with security being the main key factor, and ensure the design metrics by proposing a novel transistor-level method of logic encryption for CMOS gates. Experimental results show that, on the usage of proposed encrypted key gates, the design overheads such as area, power, delay, and energy are reduced by an average of 42.94%, 37.37%, 26.79%, and 50.96%, respectively, over the existing logic encryption-based topologies.

不可信的第三方和不可信的铸造厂突出了硬件安全在当今世界的重要性。由于半导体行业集成电路 (IC) 设计流程的全球化，必须采取硬件安全问题来防止知识产权 (IP) 盗版。逻辑加密是保护电路免受IP盗版、逆向工程和恶意篡改IC以插入木马的有效方法。研究人员提出了许多逻辑加密方法，导致电路设计参数如面积、功耗和性能的开销。本文旨在权衡这些参数，以安全性为主要关键因素，并通过提出一种新颖的晶体管级 CMOS 门逻辑加密方法来确保设计指标。实验结果表明，