In this paper, the analytical modeling of surface potential, threshold voltage, subthreshold swing, and drain-induced barrier lowering (DIBL) of negative capacitance (NC) silicon nanotube FETs (SiNTFETs) are presented. The surface potential model is obtained by solving the 3D Poisson's equation in cylindrical coordinates with the suitable boundary conditions in the channel region. The impact of the drain coupling capacitance (C_d) on the internal gate voltage (V_int) is included in the model as it influences the performance of NC FETs. Negative DIBL property resulting from the NC effect is demonstrated with the help of surface potential and threshold voltage modeling. The thickness of the ferroelectric (t_fe) and ferroelectric parameter (α) are varied to observe the impact of NC on device performance. The threshold voltage (V_th) roll-off and subthreshold swing (SS) of NC SiNTFET are presented at variable channel length (L). A minimum SS of 46.81 mV/decade is obtained in the range of L with a t_fe of 2 nm which is well below the Boltzmann limit of 60 mV/decade. A positive V_th roll-off is observed in NC SiNTFETs with a t_fe of 2 nm at a higher drain voltage (V_ds) of 0.7 V owing to negative DIBL. The model results are in good agreement with the TCAD simulation results.

在本文中，介绍了负电容 (NC) 硅纳米管 FET (SiNTFET) 的表面电位、阈值电压、亚阈值摆幅和漏极感应势垒降低 (DIBL) 的分析模型。表面电势模型是通过在通道区域中使用合适的边界条件求解圆柱坐标系中的 3D 泊松方程获得的。模型中包含漏极耦合电容 ( Cd ) 对内部栅极电压 ( _Vint )_的影响，因为它会影响 NC FET 的性能。在表面电位和阈值电压建模的帮助下证明了 NC 效应导致的负 DIBL 特性。铁电体的厚度（t _fe) 和铁电参数 ( α ) 变化以观察 NC 对器件性能的影响。_{NC SiNTFET}的阈值电压 ( Vth ) 滚降和亚阈值摆幅 (SS) 在可变通道长度 ( L ) 下呈现。在tfe_{为2 nm 的}L范围内获得了 46.81 mV/decade 的最小 SS，这远低于 60 mV/decade 的玻尔兹曼极限。在 NC SiNTFET 中观察到正V _th滚降，t _fe为 2 nm，漏极电压较高 ( V _ds) 的 0.7 V 由于负 DIBL。模型结果与 TCAD 仿真结果吻合较好。