A two-stage 180-nm CMOS wideband (14–22 GHz) power amplifier (PA) with a superimposed staggered technique and defected-ground-structure (DGS) inductors is introduced, where a wideband peaking main stage is designed at the center frequency; then, a superimposed dual-band (SDB) driver stage is proposed to obtain the optimally flat gain response over the whole bandwidth (BW). Also, DGS inductors are used to enhance the power added efficiency (PAE) of the implemented PA by decreasing the matching circuits’ insertion losses. The proposed PA achieved a power gain of 12 dB at a total chip area of 0.564 mm2. Also, at the center frequency, it achieved a saturated output power of 16.6 dBm exhibiting the smallest reported amplitude-to-phase (AM-PM) distortion (2.1°) and group delay (GD) variations (±66 ps). Finally, it gives among the highest fractional bandwidth (FBW) (44.4%) and the PAE (18.7%) so far. Also, it achieves an error vector magnitude of −25 dB at 9.3-dBm output power for a 400-MHz 5G-NR signal.

中文翻译：

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采用叠加双频段配置和 DGS 电感器、FBW 为 44.4% 的高 PAE CMOS 功率放大器


介绍了一种采用叠加交错技术和缺陷接地结构 (DGS) 电感器的两级 180 nm CMOS 宽带 (14–22 GHz) 功率放大器 (PA)，其中宽带峰值主级设计在中心频率;然后，提出了叠加双频带（SDB）驱动级，以获得整个带宽（BW）上的最佳平坦增益响应。此外，DGS 电感器还用于通过降低匹配电路的插入损耗来提高所实施 PA 的功率附加效率 (PAE)。所提出的 PA 在 0.564 mm2 的总芯片面积上实现了 12 dB 的功率增益。此外，在中心频率处，它实现了 16.6 dBm 的饱和输出功率，表现出报告的最小幅相 (AM-PM) 失真 (2.1°) 和群延迟 (GD) 变化 (±66 ps)。最后，它给出了迄今为止最高的分数带宽 (FBW) (44.4%) 和 PAE (18.7%)。此外，对于 400 MHz 5G-NR 信号，它在 9.3 dBm 输出功率下实现了 −25 dB 的误差矢量幅度。