Large-Scale Ultrathin Channel Nanosheet-Stacked CFET Based on CVD 1L MoS2/WSe2,Advanced Electronic Materials

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Large-Scale Ultrathin Channel Nanosheet-Stacked CFET Based on CVD 1L MoS2/WSe2
Advanced Electronic Materials ( IF 5.3 ) Pub Date : 2022-11-15 , DOI: 10.1002/aelm.202200722
Menggan Liu _{1,

2} , Jiebin Niu _{1,

2} , Guanhua Yang _{1,

2,

3} , Kaifei Chen _{1,

2} , Wendong Lu ₁ , Fuxi Liao ₁ , Congyan Lu _{1,

2} , Nianduan Lu _{1,

2} , Ling Li _{1,

2,

3}

Affiliation

Nanosheet (NS) vertical-stacked complementary field-effect transistors (CFETs), where the NS n-FET and NS p-FET are vertically stacked and controlled using a common gate, would result in maximum device footprint reduction. However, silicon-based transistor will become invalid due to mobility degradation and leakage current rising when scaling the thickness of channel and dielectric. Here, it is experimentally demonstrated that CFET can scaling down to 1 nm channel thickness with excellent performance, where chemical vapor deposition (CVD) one layer (1L) WSe₂ p-type NS FET is vertically stacked on top of CVD 1L MoS₂ n-type NS FET. Bottom MoS₂ NS FET achieves high on-state current of I_ON = 3.3 × 10⁻⁵ A µm µm⁻¹ and low off-state current of I_OFF = 3.3 × 10⁻¹³ A µm µm⁻¹ at V_DS = 0.7 V, with the subthreshold swing reaching 80 mV dec⁻¹. Top WSe₂ NS FET achieves high on-state current of I_ON = 1.2 × 10⁻⁵ A µm µm⁻¹ and I_OFF = 4 × 10⁻¹¹ A µm µm⁻¹ at V_DS = −0.7 V, while the subthreshold swing reaching 150 mV dec⁻¹. Statistical data of 22 CFET devices demonstrate excellent uniformity toward large-area applications. The CFET based on large-scale 2D materials breaks the limit of channel scaling and provides a technological base for future high-performance and low-power electronics.

中文翻译：

基于 CVD 1L MoS2/WSe2 的大规模超薄通道纳米片堆叠 CFET

纳米片 (NS) 垂直堆叠互补场效应晶体管 (CFET)，其中 NS n-FET 和 NS p-FET 垂直堆叠并使用公共栅极进行控制，将最大限度地减少器件占地面积。然而，硅基晶体管在缩放沟道和电介质的厚度时会由于迁移率下降和漏电流上升而失效。在这里，实验证明 CFET 可以按比例缩小到 1 nm 通道厚度并具有出色的性能，其中化学气相沉积 (CVD) 一层 (1L) WSe ₂ p 型 NS FET 垂直堆叠在 CVD 1L MoS ₂ n的顶部型 NS FET。底部的 MoS _{2 NS FET 实现了}I _ON = 3.3 × 10 ⁻⁵的高导通电流A µm µm ^-1和低关断电流I _OFF = 3.3 × 10 ^-13 A µm µm ^-1在V _DS = 0.7 V 时，亚阈值摆幅达到 80 mV dec ^-1。Top WSe _{2 NS FET 在 V}_{DS = −0.7 V 时实现}I _ON = 1.2 × 10 ⁻⁵ A µm µm ⁻¹和I _OFF = 4 × 10 ⁻¹¹ A µm µm ⁻¹的高导通电流，而亚阈值摆幅达到 150 mV dec ⁻¹. 22 个 CFET 器件的统计数据显示出对大面积应用具有出色的均匀性。基于大尺寸二维材料的CFET打破了通道缩放的限制，为未来高性能低功耗电子产品提供了技术基础。

更新日期：2022-11-15

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