<br>晶圆间键合制造中切割工艺的翘曲减少和热应力研究,IEEE Transactions on Electron Devices

当前位置： X-MOL 学术 › IEEE Trans. Elect. Dev. › 论文详情

Our official English website, www.x-mol.net, welcomes your feedback! (Note: you will need to create a separate account there.)

晶圆间键合制造中切割工艺的翘曲减少和热应力研究
IEEE Transactions on Electron Devices ( IF 2.9 ) Pub Date : 10-5-2022 , DOI: 10.1109/ted.2022.3209140
Wei Feng ₁ , Haruo Shimamoto ₁ , Tsuyoshi Kawagoe ₂ , Ichirou Honma ₂ , Masato Yamasaki ₂ , Fumitake Okutsu ₂ , Takatoshi Masuda ₂ , Katsuya Kikuchi ₁

Affiliation

我们通过实验和全晶圆模型模拟成功研究了晶圆对晶圆（W2W）键合后的翘曲。此外，通过将切割间距从芯片尺寸的一个间距改变为四分之一间距，研究了切割工艺对减少翘曲和键合晶圆热应力的影响。当切割间距减少到四分之一间距时，观察到键合晶圆翘曲减少了 27.8%。采用代表性体积元（RVE）方法进行仿真建立了完整的晶圆模型，并通过与测量的晶圆翘曲数据的良好一致性进行了验证。键合晶圆的径向应力分布表示动态随机存取存储器 (DRAM) 层的拉应力以及顶部和底部晶圆的 DRAM/Si 基板界面的压应力，这是由于 DRAM 层在温度从最高温度下降的情况下收缩而产生的。制造温度至室温。不同间距切割工艺后的径向应力分布表明，一间距切割和半间距切割后的应力水平相似。当切割间距减小到四分之一值时，压应力减小，相应地导致翘曲减少。通过小切割间距中断晶片的连续性所释放的应力被揭示是晶片翘曲减少的根源。这项研究为减少翘曲的切割街间距提供了指导，对于优化器件布局设计很有用。

"点击查看英文标题和摘要"

Warpage Reduction and Thermal Stress Study of Dicing Process in Wafer-to-Wafer Bonding Fabrication

We successfully study the warpage after wafer-to-wafer (W2W) bonding by the experiments and the full wafer model simulation. Furthermore, the effect of the dicing process on the warpage reduction and the thermal stress of bonded wafer are investigated by varying the dicing pitch from a one pitch as chip size to a quarter pitch. When the dicing pitch decreases to a quarter pitch, the bonded wafer warpage is observed to decrease by 27.8%. A full wafer model is established with the representative volume element (RVE) method in simulation and validated by good agreement with the measured wafer warpage data. The radial stress distribution of bonded wafer indicates tensile stress for the dynamic random access memory (DRAM) layers and compressive stress for the DRAM/Si substrate interface of top and bottom wafers due to the shrinkage of the DRAM layers under the temperature decrease from its high fabrication temperature to the room temperature. The radial stress distribution after the dicing process with different pitches indicates a similar stress level after one-pitch dicing and half-pitch dicing. When the dicing pitch decreases to a quarter value, the compressive stress decreases, correspondingly resulting in a warpage reduction. The stress released by interrupting the continuity of the wafer with a small dicing pitch is revealed to be the origin of wafer warpage reduction. This study provides a guideline of dicing street pitch for warpage reduction and is useful for optimizing the device layout design.

更新日期：2024-08-26

点击分享查看原文

点击收藏

阅读更多本刊新发论文本刊介绍/投稿指南