Arithmetic operations play a substantial role in many applications, such as image processing. In image processing applications, a multiplier is a predominantly used arithmetic operation. In recent designs of Approximate Multipliers (AMs), the design metrics of multipliers are made better at the cost of Error metrics and vice versa. So, in order to balance both the error and design metrics in a multiplier design with increasing the width of the input operands, a Rounding-based AM (RAM) using a modified Karatsuba algorithm is proposed, in which the usage of the number of multipliers is reduced. Small multipliers are used with shifting and rounding operations so as to reduce power consumption, delay, and area. Both the prior and proposed AMs are later synthesized in Verilog HDL using the Cadence RTL compiler. The simulation results divulge that the proposed RAM of sizes 8 and 16 bits are designed and their performance metrics in terms of delay, and area are decreased on an average of 61.8%, and 52.6% with an improvement in power by 53.8% for 8-bit AM and also the delay, area and power are reduced on an average of 53.2%, 59.7%, and 25% for a 16-bit AM’s, in comparison with the prior AMs. The proposed RAM is demonstrated using the smoothening image application, and we observe that an improved image quality is obtained with SSIM and PSNR of the ISFA incorporated proposed RAM within the range of 1.44%—84.47% and 0.28%- 24.4%, over the ISFA incorporated existing AMs.