Power-handling capability of bulk CMOS-based single-pole double-throw (SPDT) switch operating in millimeter-wave (mm-wave) and subterahertz region is significantly limited by the reduced threshold voltage of deeply scaled transistors. A unique design technique based on impedance transformation network (ITN) is presented in this work, which improves 1-dB compression point, namely P1dB, without deteriorating other performance. To prove the presented solution is valid, a 70–100-GHz switch is designed and implemented in a 55-nm bulk CMOS technology. At 90 GHz, it achieves a measured P1dB of 15 dBm, an insertion loss (IL) of 3.5 dB, and an isolation (ISO) of 18 dB. The total area of the chip is only 0.14 mm 2 .

中文翻译：

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采用 55 nm Bulk CMOS 且具有 15 dBm P1dB 的 W 波段 SPDT 开关


在毫米波 (mm-wave) 和亚赫兹区域运行的基于体 CMOS 的单刀双掷 (SPDT) 开关的功率处理能力受到深度尺寸晶体管阈值电压降低的严重限制。这项工作提出了一种基于阻抗变换网络（ITN）的独特设计技术，它提高了 1 dB 压缩点，即 P1dB，而不会降低其他性能。为了证明所提出的解决方案的有效性，我们采用 55 nm 体 CMOS 技术设计并实现了 70–100 GHz 开关。在 90 GHz 时，其测量 P1dB 为 15 dBm，插入损耗 (IL) 为 3.5 dB，隔离度 (ISO) 为 18 dB。芯片总面积仅为0.14mm 2 。