A design methodology of a CC -band high-efficiency Doherty power amplifier (DPA) with harmonic control is presented in this letter. The equivalent parasitic network (EPN) of the packaged device is constructed by a deembedding technique. The phase delay caused by the transistor parasitics is calculated using the scattering matrix of the EPN. Besides, the influence of the phase delay on DPA design is analyzed. To improve the efficiency at output back-off (OBO) power level, postmatching network (PMN) is used to control the second harmonic. A high-efficiency DPA working over 6.4–7.1 GHz is implemented, fabricated, and measured. The DPA delivers a saturation output power ( PsatP_{\text {sat}} ) of 39.6–41.6 dBm. Meanwhile, the drain efficiencies in the interested frequency band are 45.1%–53.2% and 34.5%–43.1% at the PsatP_{\text {sat}} and 6-dB OBO power levels, respectively.

中文翻译：

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具有谐波控制的C波段高效Doherty功率放大器的设计


这封信介绍了一种具有谐波控制功能的 CC 频段高效 Doherty 功率放大器 (DPA) 的设计方法。封装器件的等效寄生网络（EPN）是通过去嵌入技术构建的。使用 EPN 的散射矩阵计算由晶体管寄生效应引起的相位延迟。此外，还分析了相位延迟对DPA设计的影响。为了提高输出回退 (OBO) 功率电平的效率，使用后匹配网络 (PMN) 来控制二次谐波。实现、制造和测量了工作频率为 6.4–7.1 GHz 的高效 DPA。 DPA 提供 39.6–41.6 dBm 的饱和输出功率 ( PsatP_{\text {sat}} )。同时，在 PsatP_{\text {sat}} 和 6 dB OBO 功率水平下，感兴趣频段的漏极效率分别为 45.1%–53.2% 和 34.5%–43.1%。