This letter introduces a novel phase detector (PD) for suppressing the reference spur in a 40 GHz integer- NN phase-locked loop (PLL). Coined as a spur-compensation phase detector (SCPD), the proposed SCPD duplicates itself to an auxiliary path for an edge-combined phase alignment, such that the spurs generated by the two paths mutually compensate for each other, achieving a net effect of spur canceling. Implemented in a 40-nm CMOS technology, the proposed PLL shows less than −71.4-dBc reference spur, −98- and −117-dBc/Hz phase noise at 1- and 10-MHz offset, respectively, and a minimum rms jitter of 114 fs (10 k–100 MHz). It consumes 23.4-mW power from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB.

中文翻译：

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具有杂散补偿相位检测器的 23.4 mW —72 dBc 参考杂散 40 GHz CMOS PLL


这封信介绍了一种新颖的鉴相器 (PD)，用于抑制 40 GHz 整数 NN 锁相环 (PLL) 中的参考杂散。所提出的 SCPD 被称为杂散补偿相位检测器 (SCPD)，将自身复制到辅助路径以进行边缘组合相位对齐，使得两个路径生成的杂散相互补偿，从而实现杂散的净效应取消。所提出的 PLL 采用 40 nm CMOS 技术实现，在 1 MHz 和 10 MHz 偏移下分别具有低于 −71.4 dBc 的参考杂散、−98 dBc/Hz 和 −117 dBc/Hz 的相位噪声，以及最小均方根抖动114 fs (10 k–100 MHz)。它通过 1.1V 电源消耗 23.4mW 功率，导致品质因数 (FoM) 为 −245dB。