Fabrication Strategies of Metal–Ferroelectric–Insulator–Silicon Gate Stacks Using Ferroelectric Hf–Zr–O and High-k HfO2 Insulator Layers for Securing Robust Ferroelectric Memory Characteristics,ACS Applied Electronic Materials

当前位置： X-MOL 学术 › ACS Appl. Electron. Mater. › 论文详情

Our official English website, www.x-mol.net, welcomes your feedback! (Note: you will need to create a separate account there.)

Fabrication Strategies of Metal–Ferroelectric–Insulator–Silicon Gate Stacks Using Ferroelectric Hf–Zr–O and High-k HfO2 Insulator Layers for Securing Robust Ferroelectric Memory Characteristics
ACS Applied Electronic Materials ( IF 4.3 ) Pub Date : 2022-05-23 , DOI: 10.1021/acsaelm.2c00402
Jin-Ju Kim ₁ , Seung-Eon Moon ₂ , Sung-Min Yoon ₁

Affiliation

Metal–ferroelectric–insulator–Si (MFIS) gate stack structures were fabricated and characterized to investigate the optimum process indicators when HfO₂-based thin films were exploited as the ferroelectric layer (FL) for the ferroelectric-field-effect-driven nonvolatile memory operations. The interfacial transition layer thicknesses of the metal–insulator–semiconductor capacitors using high dielectric constant (high-k) insulator layers (ILs) were preliminarily examined to be approximately 0.7 and 0.5 nm for the Pt/HfO₂/Si and Pt/Al₂O₃/Si capacitors, respectively, which corresponded to Hf silicate and amorphous SiO₂. As the result, the introduction of HfO₂ IL was verified to enhance the capacitance coupling ratio 1.7 times higher than that by the use of Al₂O₃ IL for the MFIS devices. Alternatively, among the fabricated MFIS capacitors with various combinations of high-k ILs and HfO₂-based FLs, the counterclockwise hysteresis loops supported by ferroelectric field effects in the C–V curves were obtained only from the devices employing the HfZrO (HZO) FLs and HfO₂ ILs. Especially, when the film thicknesses of the HZO FL and HfO₂ IL were controlled to be 20 and 5 nm, respectively, the MFIS capacitor exhibited the ferroelectric memory window as large as 2.1 V and the long-term retention with a charge loss of only 11% after a lapse of time for 10⁴ s. These differences in the device characteristics among the controlled devices originated from the combined effects of voltage distribution between the FLs and ILs, crystallinity of the FL prepared on various ILs, and capacitance coupling ratio, which could be suggested as important control parameters to optimize the memory operations of MFIS devices.

中文翻译：

使用铁电 Hf-Zr-O 和高 k HfO2 绝缘层的金属-铁电-绝缘体-硅栅堆叠的制造策略，以确保稳健的铁电存储器特性

制造金属-铁电-绝缘体-Si (MFIS) 栅堆叠结构并对其进行表征，以研究将 HfO ₂基薄膜用作铁电场效应驱动的非易失性存储器的铁电层 (FL)时的最佳工艺指标操作。_{对于 Pt/HfO 2} /Si 和 Pt/Al ₂，使用高介电常数 (high-k) 绝缘层 (ILs) 的金属-绝缘体-半导体电容器的界面过渡层厚度初步检测为大约 0.7 和 0.5 nm O ₃ /Si 电容器分别对应于Hf 硅酸盐和非晶SiO ₂。因此，引入 HfO ₂经证实，IL 可将电容耦合比提高 1.7 倍，比使用 Al ₂ O ₃ IL 的 MFIS 器件高出 1.7 倍。或者，在制造的具有高 k IL 和基于 HfO ₂的 FL 的各种组合的 MFIS 电容器中，仅从采用 HfZrO (HZO) FL 的器件中获得由C - V曲线中的铁电场效应支持的逆时针磁滞回线和 HfO ₂ IL。_{特别是，当 HZO FL 和 HfO 2}的膜厚^{IL分别控制在20和5 nm，MFIS电容器表现出高达2.1 V的铁电记忆窗口和10 4} s后电荷损失仅为11%的长期保留。受控器件之间器件特性的这些差异源于 FL 和 IL 之间的电压分布、在各种 IL 上制备的 FL 的结晶度和电容耦合比的综合影响，这可以作为优化存储器的重要控制参数。 MFIS 设备的操作。

更新日期：2022-05-23

点击分享查看原文

点击收藏

阅读更多本刊新发论文本刊介绍/投稿指南