In addition to low noise figure (NF) and high gain, 1-dB compression point (P1dB) and the input third-order intercept point (IIP3) are critical in the design of a high dynamic range low-noise amplifier (LNA). An improved and optimized highly linear LNA configured by a differential quartet structure is proposed. The differential quartet topology is more linear than the conventional differential topology. The differential trans-conductance of the differential quartet topology is smooth for a wider range of input voltage variations. The equations for the performance parameters of the LNA are extracted. Moreover, a specific step-by-step method is described for this topology. Using this, regular method leads to simultaneous improvements in the specifications of the amplifier. A 24GHz LNA is designed in a standard 180 nm CMOS technology. The layout parasitic effects are extracted using electromagnetic (EM) simulation. The optimized LNA achieves an input/output return loss of \(- 15.6/ - 11.7\) dB. The simulation results show a peak S21 of 10.27 dB at 23.72 GHz, an NF of 3.3 dB, and a P1dB of − 5 dB at 24 GHz. Furthermore, IIP3 is 11.68 dBm, the power consumption at the 3V supply voltage is 17.8 mW, and the core layout size is 580 μm × 640 μm.