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Dual-Ferroelectric-Coupling-Engineered Two-Dimensional Transistors for Multifunctional In-Memory Computing
ACS Nano ( IF 15.8 ) Pub Date : 2022-02-11 , DOI: 10.1021/acsnano.2c00079 Zheng-Dong Luo 1 , Siqing Zhang 1 , Yan Liu 1 , Dawei Zhang 2 , Xuetao Gan 3 , Jan Seidel 2, 4 , Yang Liu 5 , Genquan Han 1, 6 , Marin Alexe 7 , Yue Hao 1
ACS Nano ( IF 15.8 ) Pub Date : 2022-02-11 , DOI: 10.1021/acsnano.2c00079 Zheng-Dong Luo 1 , Siqing Zhang 1 , Yan Liu 1 , Dawei Zhang 2 , Xuetao Gan 3 , Jan Seidel 2, 4 , Yang Liu 5 , Genquan Han 1, 6 , Marin Alexe 7 , Yue Hao 1
Affiliation
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In-memory computing featuring a radical departure from the von Neumann architecture is promising to substantially reduce the energy and time consumption for data-intensive computation. With the increasing challenges facing silicon complementary metal-oxide-semiconductor (CMOS) technology, developing in-memory computing hardware would require a different platform to deliver significantly enhanced functionalities at the material and device level. Here, we explore a dual-gate two-dimensional ferroelectric field-effect transistor (2D FeFET) as a basic device to form both nonvolatile logic gates and artificial synapses, addressing in-memory computing simultaneously in digital and analog spaces. Through diversifying the electrostatic behaviors in 2D transistors with the dual-ferroelectric-coupling effect, rich logic functionalities including linear (AND, OR) and nonlinear (XNOR) gates were obtained in unipolar (MoS2) and ambipolar (MoTe2) FeFETs. Combining both types of 2D FeFETs in a heterogeneous platform, an important computation circuit, i.e., a half-adder, was successfully constructed with an area-efficient two-transistor structure. Furthermore, with the same device structure, several key synaptic functions are shown at the device level, and an artificial neural network is simulated at the system level, manifesting its potential for neuromorphic computing. These findings highlight the prospects of dual-gate 2D FeFETs for the development of multifunctional in-memory computing hardware capable of both digital and analog computation.
中文翻译：
用于多功能内存计算的双铁电耦合设计二维晶体管
与冯诺依曼架构彻底背离的内存计算有望显着降低数据密集型计算的能耗和时间消耗。随着硅互补金属氧化物半导体 (CMOS) 技术面临的挑战越来越多，开发内存计算硬件将需要不同的平台来在材料和器件级别提供显着增强的功能。在这里，我们探索了双栅极二维铁电场效应晶体管 (2D FeFET) 作为基本器件，以形成非易失性逻辑门和人工突触，同时解决数字和模拟空间中的内存计算。通过利用双铁电耦合效应使二维晶体管中的静电行为多样化，丰富的逻辑功能包括线性（AND，2 ) 和双极 (MoTe 2 ) FeFET。在异构平台中结合这两种类型的 2D FeFET，成功地构建了具有面积效率的双晶体管结构的重要计算电路，即半加器。此外，在相同的设备结构下，在设备层面展示了几个关键的突触功能，并在系统层面模拟了人工神经网络，展现了其在神经形态计算方面的潜力。这些发现突出了双栅极 2D FeFET 在开发能够进行数字和模拟计算的多功能内存计算硬件方面的前景。
更新日期：2022-02-11
中文翻译：
用于多功能内存计算的双铁电耦合设计二维晶体管
与冯诺依曼架构彻底背离的内存计算有望显着降低数据密集型计算的能耗和时间消耗。随着硅互补金属氧化物半导体 (CMOS) 技术面临的挑战越来越多，开发内存计算硬件将需要不同的平台来在材料和器件级别提供显着增强的功能。在这里，我们探索了双栅极二维铁电场效应晶体管 (2D FeFET) 作为基本器件，以形成非易失性逻辑门和人工突触，同时解决数字和模拟空间中的内存计算。通过利用双铁电耦合效应使二维晶体管中的静电行为多样化，丰富的逻辑功能包括线性（AND，2 ) 和双极 (MoTe 2 ) FeFET。在异构平台中结合这两种类型的 2D FeFET，成功地构建了具有面积效率的双晶体管结构的重要计算电路，即半加器。此外，在相同的设备结构下，在设备层面展示了几个关键的突触功能，并在系统层面模拟了人工神经网络，展现了其在神经形态计算方面的潜力。这些发现突出了双栅极 2D FeFET 在开发能够进行数字和模拟计算的多功能内存计算硬件方面的前景。
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