Driven by technologies such as machine learning, artificial intelligence, and internet of things, the energy efficiency and throughput limitations of the von Neumann architecture are becoming more and more serious. As a new type of computer architecture, computing-in-memory is an alternative approach to alleviate the von Neumann bottleneck. Here, we have demonstrated two kinds of computing-in-memory designs based on two-surface-channel MoS₂ transistors: symmetrical 4T2R Static Random-Access Memory (SRAM) cell and skewed 3T3R SRAM cell, where the symmetrical SRAM cell can realize in-memory XNOR/XOR computations and the skewed SRAM cell can achieve in-memory NAND/NOR computations. Furthermore, since both the memory and computing units are based on two-surface-channel transistors with high area efficiency, the two proposed computing-in-memory SRAM cells consume fewer transistors, suggesting a potential application in highly area-efficient and multifunctional computing chips.

在机器学习、人工智能、物联网等技术的推动下，冯诺依曼架构的能效和吞吐量限制越来越严重。作为一种新型的计算机体系结构，内存计算是缓解冯诺依曼瓶颈的一种替代方法。在这里，我们展示了两种基于双表面通道 MoS ₂晶体管的内存计算设计：对称 4T2R 静态随机存取存储器 (SRAM) 单元和偏斜 3T3R SRAM 单元，其中对称 SRAM 单元可以在-memory XNOR / XOR计算和倾斜的 SRAM 单元可以实现 in-memory NAND / NOR计算。此外，由于存储器和计算单元均基于面积效率高的双表面沟道晶体管，因此提出的两种内存计算SRAM单元消耗的晶体管更少，表明在高面积效率和多功能计算芯片中的潜在应用.