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A novel PVT-variation-tolerant Schmitt-trigger-based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub-threshold region
International Journal of Circuit Theory and Applications ( IF 1.8 ) Pub Date : 2021-09-05 , DOI: 10.1002/cta.3134 Monica Gupta 1, 2 , Kirti Gupta 2 , Neeta Pandey 1
International Journal of Circuit Theory and Applications ( IF 1.8 ) Pub Date : 2021-09-05 , DOI: 10.1002/cta.3134 Monica Gupta 1, 2 , Kirti Gupta 2 , Neeta Pandey 1
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This paper presents a process voltage temperature (PVT)-variation-tolerant Schmitt-trigger-based 12T SRAM cell at 32 nm. The cell uses a modified Schmitt-trigger action in all operating modes for performance improvement, a characteristic that is not exhibited by existing SRAM cells. The action improves the stability of stored data in read and hold modes and assists the write process to enable a faster and low-voltage write operation. Additionally, the cell uses negative bitline technique and fully-gated grounded scheme for achieving further improvement in write ability and ION/IOFF ratio. The proposed cell shows 34.9% reduced deviation in switching threshold voltage in comparison to conventional structure. Further, improvement of up to 211% in write ability and 169% in ION/IOFF ratio is obtained over existing SRAM cells operating in sub-threshold region. The cell takes up to 86% and 99% lesser read and write access time, respectively. The Monte-Carlo simulations show the robust performance of proposed cell. The cell has reduced write, read, and hold failure probabilities resulting in overall Vmin of 425 mV, which is the least among the cells considered for comparison, thus making it an amenable design suitable for sub-threshold operation under PVT-variations.
中文翻译：
一种新型的基于 PVT 变化的施密特触发器 12T SRAM 单元，在亚阈值区域具有改进的写入能力和高 ION/IOFF 比
本文介绍了一种基于 32 nm 工艺电压温度 (PVT) 变化容忍施密特触发器的 12T SRAM 单元。该单元在所有操作模式下都使用改进的施密特触发器来提高性能，这是现有 SRAM 单元不具备的特性。该操作提高了读取和保持模式下存储数据的稳定性，并协助写入过程以实现更快的低电压写入操作。此外，该单元使用负位线技术和全门控接地方案，以进一步提高写入能力和 I ON / I OFF比。与传统结构相比，所提出的单元显示开关阈值电压的偏差减少了 34.9%。此外，写入能力提高了 211%，I 提高了 169%在亚阈值区域中运行的现有 SRAM 单元上获得了ON / I OFF比。该单元的读写访问时间分别减少了 86% 和 99%。Monte-Carlo 模拟显示了所提出的单元的稳健性能。该单元降低了写入、读取和保持失败的概率，导致整体 Vmin 为 425 mV，这是考虑进行比较的单元中最少的，因此使其成为适合 PVT 变化下的亚阈值操作的设计。
更新日期：2021-09-05
中文翻译：
一种新型的基于 PVT 变化的施密特触发器 12T SRAM 单元，在亚阈值区域具有改进的写入能力和高 ION/IOFF 比
本文介绍了一种基于 32 nm 工艺电压温度 (PVT) 变化容忍施密特触发器的 12T SRAM 单元。该单元在所有操作模式下都使用改进的施密特触发器来提高性能，这是现有 SRAM 单元不具备的特性。该操作提高了读取和保持模式下存储数据的稳定性，并协助写入过程以实现更快的低电压写入操作。此外，该单元使用负位线技术和全门控接地方案，以进一步提高写入能力和 I ON / I OFF比。与传统结构相比，所提出的单元显示开关阈值电压的偏差减少了 34.9%。此外，写入能力提高了 211%，I 提高了 169%在亚阈值区域中运行的现有 SRAM 单元上获得了ON / I OFF比。该单元的读写访问时间分别减少了 86% 和 99%。Monte-Carlo 模拟显示了所提出的单元的稳健性能。该单元降低了写入、读取和保持失败的概率，导致整体 Vmin 为 425 mV，这是考虑进行比较的单元中最少的，因此使其成为适合 PVT 变化下的亚阈值操作的设计。
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