In this study, a gate-stack engineering technique is proposed as a means of improving the performance of a 28 nm low-power (LP) high-k/metal-gate (HK/MG) device. In detail, it was experimentally verified that HfSiO thin films can replace HfSiON congeners, where the latter are known to have a good thermal budget and/or electrical characteristics, to boost the device performance under a limited thermal budget. TiN engineering for the gate-stack in the 28 nm LP HK/MG device was used to suppress the gate leakage current. Using the proposed fabrication method, the on/off current ratio (I_on/I_off) was improved for a given target I_on, and the gate leakage current was appropriately suppressed. Comparing the process-of-record device against the 28 nm LP HK/MG device, the thickness of the electrical oxide layer in the new device was reduced by 3.1% in the case of n-type field effect transistors and by 10% for p-type field effect transistors. In addition, the reliability (e.g., bias temperature instability, hot carrier injury, and time-dependent dielectric breakdown) of the new device was evaluated, and it was observed that there was no conspicuous risk. Therefore, the HfSiO film can afford reliable performance enhancement when employed in the 28 nm LP HK/MG device with a limited thermal budget.

中文翻译：

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提高 28 nm 低功耗高 k/金属栅极器件性能的门堆栈工程

在这项研究中，提出了一种栅堆叠工程技术，作为提高 28 nm 低功率 (LP) 高 k/金属栅 (HK/MG) 器件性能的一种手段。详细地，实验证实 HfSiO 薄膜可以替代 HfSiON 同类物，其中后者已知具有良好的热预算和/或电气特性，以在有限的热预算下提高器件性能。28 nm LP HK/MG 器件中栅极堆叠的 TiN 工程用于抑制栅极漏电流。使用所提出的制造方法，对于给定的目标I _on提高了开/关电流比（I _on / I _off），并适当抑制栅极漏电流。将记录工艺器件与 28 nm LP HK/MG 器件进行比较，在 n 型场效应晶体管的情况下，新器件中电氧化层的厚度减少了 3.1%，而 p 减少了 10%型场效应晶体管。此外，还评估了新器件的可靠性（例如，偏置温度不稳定性、热载流子损伤和时间依赖性介电击穿），并观察到没有明显的风险。因此，当在热预算有限的 28 nm LP HK/MG 器件中使用 HfSiO 薄膜时，可以提供可靠的性能增强。