In this paper, novel circuits for XOR/XNOR and simultaneous XOR–XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. We also propose six new hybrid 1-bit full-adder (FA) circuits based on the novel full-swing XOR–XNOR or XOR/XNOR gates. Each of the proposed circuits has its own merits in terms of speed, power consumption, power-delay product (PDP), driving ability, and so on. To investigate the performance of the proposed designs, extensive HSPICE and Cadence Virtuoso simulations are performed. The simulation results, based on the 65-nm CMOS process technology model, indicate that the proposed designs have superior speed and power against other FA designs. A new transistor sizing method is presented to optimize the PDP of the circuits. In the proposed method, the numerical computation particle swarm optimization algorithm is used to achieve the desired value for optimum PDP with fewer iterations. The proposed circuits are investigated in terms of variations of the supply and threshold voltages, output capacitance, input noise immunity, and the size of transistors.

中文翻译：

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通过探索新的 XOR 和 XNOR 门的低功耗和快速全加器

在本文中，提出了用于 XOR/XNOR 和同步 XOR-XNOR 功能的新型电路。由于低输出电容和低短路功耗，所提出的电路在功耗和延迟方面进行了高度优化。我们还提出了六个基于新型全摆幅 XOR–XNOR 或 XOR/XNOR 门的新型混合 1 位全加器 (FA) 电路。每个提议的电路在速度、功耗、功率延迟积 (PDP)、驱动能力等方面都有自己的优点。为了研究所提议设计的性能，进行了广泛的 HSPICE 和 Cadence Virtuoso 模拟。基于 65 纳米 CMOS 工艺技术模型的仿真结果表明，与其他 FA 设计相比，所提出的设计具有卓越的速度和功率。提出了一种新的晶体管尺寸调整方法来优化电路的 PDP。在所提出的方法中，数值计算粒子群优化算法用于以较少的迭代获得最优PDP的期望值。根据电源和阈值电压、输出电容、输入抗扰度和晶体管尺寸的变化对所提出的电路进行了研究。