The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density (and therefore resolution) over that of speed, where the most widely used refresh rates fall between 25-240 Hz. Therefore, memristor-CMOS logic is a promising fit for peripheral IO logic in active matrix displays. In this paper, we design and implement a ternary 1-3 line decoder and a ternary 2-9 line decoder which are used to program a seven segment LED display. SPICE simulations are conducted in a 50-nm process, and the decoders are synthesized on an Altera Cyclone IV field-programmable gate array (FPGA) development board which implements a ternary memristor model designed in Quartus II. We compare our hardware results to a binary coded decimal (BCD)-to-seven segment display decoder, and show our memristor-CMOS approach reduces the total IO power consumption by a factor of approximately 6 times at a maximum synthesizable frequency of 293.77MHz. Although the speed is approximately half of the native built-in BCD-to-seven decoder, the comparatively slow refresh rates of typical microdisplays indicate this to be a tolerable trade-off, which promotes data density over speed.

中文翻译：

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三元忆阻器-CMOS解码器的FPGA综合

忆阻器-CMOS逻辑门的兼容应用一直难以捉摸，因为低速开关速度和电阻耗散抵消了数据密度带来的好处。有源微型显示器通常会优先考虑像素密度（以及分辨率），而不是速度，后者最常用的刷新率介于25-240 Hz之间。因此，忆阻器CMOS逻辑非常适合有源矩阵显示器中的外围IO逻辑。在本文中，我们设计并实现了用于编程七段式LED显示屏的三元1-3线解码器和三元2-9线解码器。SPICE仿真是在50nm工艺中进行的，解码器在Altera Cyclone IV现场可编程门阵列（FPGA）开发板上合成，该开发板上实现了Quartus II中设计的三元忆阻器模型。我们将硬件结果与二进制编码的十进制（BCD）到七段显示解码器进行了比较，并证明了忆阻器CMOS方法在293.77MHz的最大可合成频率下将总IO功耗降低了大约6倍。尽管速度大约是原生内置BCD到7解码器的一半，但是典型的微型显示器的刷新速度相对较慢，这表明这是可以容忍的折衷，这会提高速度上的数据密度。