Sub-5 nm Monolayer MoS2 Transistors toward Low-Power Devices,ACS Applied Electronic Materials

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Sub-5 nm Monolayer MoS2 Transistors toward Low-Power Devices
ACS Applied Electronic Materials ( IF 4.3 ) Pub Date : 2021-03-15 , DOI: 10.1021/acsaelm.0c00840
Han Zhang _{1,

2} , Bowen Shi ₂ , Lin Xu ₃ , Junfeng Yan ₁ , Wu Zhao ₁ , Zhiyong Zhang ₁ , Zhiyong Zhang ₃ , Jing Lu _{2,

3,

4,

5}

Affiliation

Inspired by the recent achievements of the two-dimensional (2D) sub-5 nm MoS₂ field effect transistors (FETs), we use the ab initio quantum-transport methods to simulate the transport properties of the sub-5 nm gate-length monolayer (ML) MoS₂ MOSFETs. We find that the ML MoS₂ double-gated MOSFETs (DGFETs) with the 1, 3, and 5 nm gate length fail to meet the on-state current requirements in the International Technology Roadmap for Semiconductors (ITRS) for high-performance (HP) devices. However, both the ML MoS₂n- and p-DGFETs with 5 nm gate length can address the requirements in the ITRS for low-power (LP) applications in terms of on-state current, effective delay time, and power-delay products (PDPs). After the introduction of the negative capacitance dielectric layer, the ML MoS₂p-DGFETs can satisfy the LP application requirements of ITRS until the gate length scales down to 3 nm. Hence, ML MoS₂ remains a potential channel candidate for LP applications in the sub-5 nm scale.

中文翻译：

面向低功率器件的亚5纳米单层MoS ₂晶体管

受二维（2D）低于5 nm的MoS ₂场效应晶体管（FET）的最新成就的启发，我们使用从头算量子传输方法来模拟低于5 nm栅长单层的传输特性（ML）MoS ₂ MOSFET。我们发现具有1,3和5 nm栅极长度的ML MoS ₂双栅极MOSFET（DGFET）不能满足《国际半导体技术路线图（ITRS）》关于高性能（HP ）设备。但是，ML MoS ₂n-和p栅极长度为5 nm的DGFET可以满足ITRS对低功率（LP）应用的要求，包括导通状态电流，有效延迟时间和功率延迟乘积（PDP）。引入负电容介电层后，ML MoS ₂p- DGFET可以满足ITRS的LP应用要求，直到栅极长度缩小到3 nm。因此，ML MoS ₂仍然是5纳米以下LP应用的潜在通道候选者。

更新日期：2021-04-27

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