The proportion of interconnect delay in the critical path on a chip is increasing and becomes over 20% in sub-10nm technologies, which means in order to capture post-Si performance accurately, the representative critical path circuit should reflect not only FEOL (front-end-of-line) but also BEOL (back-end-of-line) variations. Since the number of BEOL metal layers exceeds ten and the layers have variation on resistance and capacitance intermixed with resistance variation on vias between them, a very high dimensional design space exploration is necessary to synthesize a representative critical path circuit which is able to provide an accurate performance prediction. To this end, we propose a BEOL-aware methodology of synthesizing a representative critical path circuit, which is able to incrementally explore, starting from an initial path circuit on the post-Si target circuit, routing patterns (i.e., BEOL reconfiguring) as well as gate resizing on the path circuit. Precisely, our synthesis framework of critical path circuit integrates a set of novel techniques: (1) extracting and classifying BEOL configurations for lightening design space complexity, (2) formulating BEOL random variables for fast and accurate timing analysis, and (3) exploring alternative (ring oscillator) circuit structures for extending the applicability of our work. In summary, our synthesis framework is able to reduce the prediction error by 54% and 19% on average over that using the conventional critical path replica and using the conventional method exploiting gate sizing only, respectively.

在低于10nm的技术中，芯片上关键路径中互连延迟的比例不断增加，并超过20％，这意味着，为了准确地捕获后硅性能，代表性的关键路径电路不仅应反映FEOL（正面行尾）和BEOL（行尾）变体。由于BEOL金属层的数量超过十个，并且这些层的电阻和电容存在变化，并且它们之间的通孔之间存在电阻变化，因此必须进行非常高尺寸的设计空间探索，才能合成具有代表性的关键路径电路，从而能够提供准确的性能预测。为此，我们提出了一种BEOL感知方法，用于合成代表性的关键路径电路，该方法能够逐步探索从后硅目标电路上的初始路径电路开始，路由模式（即BEOL重新配置）以及路径电路上的门调整大小。准确地说，我们的关键路径电路综合框架集成了一组新颖的技术：（1）提取和分类BEOL配置以减轻设计空间的复杂性；（2）制定BEOL随机变量以进行快速准确的时序分析；以及（3）探索替代方法（环形振荡器）电路结构扩展我们工作的适用性。总而言之，与使用常规关键路径副本和仅使用门大小的常规方法相比，我们的综合框架平均可以将预测误差平均降低54％和19％。