Through-silicon-via (TSV) interposers using silicon and copper represent a critical element in microelectronic packaging, as they bridge between fine-pitch inputs/outputs at the integrated circuit chips to the coarser-pitch packages at the substrate. High electrical conductivity is one of the required properties, but as with the continued miniaturization of electronics, thermal expansion match between the substrate (typically silicon) and copper becomes increasingly important to avoid device failure. A CNT-Cu composite TSV interposer was fabricated envisioning microelectronic packaging applications, which demonstrates both copper-level electrical conductivity (∼2.5 × 10⁵ S/cm) and Si-level coefficient of thermal expansion (CTE) (∼7 × 10^–6/K). The CTE mismatch between CNT-Cu and Si was measured to be less than 1/5 compared with that between Cu and Si. To realize this, numerous technologies were combined. Specifically, this included the precision synthesis of vertically aligned pillars perfectly normal to the growth substrate, structural reinforcement of the CNT bundles to retain alignment during processing, electrodeposition of Cu into the interstitial spaces of the CNT pillars, and insertion of the CNT-Cu pillar arras into a prefabricated TSV substrate. Finally, the functionality of the prepared CNT-Cu TSV interposer was demonstrated for several configurations.

中文翻译：

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基于碳纳米管-铜复合材料的具有微电子封装应用的具有Cu级导电性和Si级热膨胀的硅通孔中介层

使用硅和铜的穿硅通孔（TSV）中介层是微电子封装中的关键元素，因为它们跨接在集成电路芯片上的细间距输入/输出与基板上的粗间距封装之间。高电导率是必需的特性之一，但是随着电子设备的不断小型化，基板（通常是硅）和铜之间的热膨胀匹配对于避免器件故障变得越来越重要。在设想微电子封装应用的情况下，制造了CNT-Cu复合TSV中介层，该中介层显示出铜级电导率（〜2.5×10 ⁵ S / cm）和Si级热膨胀系数（CTE）（〜7×10 ^–6）/ K）。与铜和硅之间的CTE失配相比，测得的CNT-Cu和Si之间的CTE失配小于1/5。为了实现这一点，将多种技术结合在一起。具体来说，这包括精确地合成垂直于生长衬底的垂直排列的柱子，对碳纳米管束进行结构增强以在加工过程中保持对准，将铜电沉积到碳纳米管柱子的间隙中以及插入碳纳米管-铜柱子进入预制的TSV基板。最后，展示了所制备的CNT-Cu TSV中介层的功能可用于多种配置。