Sheet Resistance Analysis of Interface-Engineered Multilayer Graphene: Mobility Versus Sheet Carrier Concentration.,ACS Applied Materials & Interfaces

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Sheet Resistance Analysis of Interface-Engineered Multilayer Graphene: Mobility Versus Sheet Carrier Concentration.
ACS Applied Materials & Interfaces ( IF 8.3 ) Pub Date : 2020-05-13 , DOI: 10.1021/acsami.0c04542
Min-Sik Kim ₁ , Minsu Kim ₁ , Suyeon Son ₂ , Seong-Yong Cho ₃ , Sangbong Lee ₁ , Dong-Kwan Won ₂ , Jaechul Ryu ₂ , Inseob Bae ₂ , Hyun-Mi Kim ₄ , Ki-Bum Kim _{1,

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Affiliation

Both interlayer-undoped and interlayer-doped multilayer graphenes were prepared by the multiple transfers of graphene layers with multiple Cu etching (either dopant-free or doped during etching) and transfer, and the effect of interface properties on the electrical properties of multilayer graphene was investigated by varying the number of layers from 1 to 12. In both the cases, the sheet resistance decreased with increasing number of layers from 700 to 104 Ω/sq for the interlayer-undoped graphene and from 280 to 25 Ω/sq for the interlayer-doped graphene. Further, Hall measurements revealed that the origins of the sheet resistance reduction in the two cases are different. In the interlayer-undoped graphene, the sheet resistance decreased because of the increase in mobility with the addition of inner layers, which has a low carrier density and a high carrier mobility. On the other hand, it decreased because of the increase in sheet carrier density in the interlayer-doped multilayer graphene. The mobility and carrier density variations in both the cases were confirmed by fitting with the model of Hall effect in the heterojunction. In addition, we found that surface property modification by the doping of the top layer and the formation of double-layer graphene with different partial coverages allow the separate control of carrier density and mobility. Our study provides an effective approach for controlling the properties of multilayer graphene for electronic applications.

中文翻译：

界面工程多层石墨烯的薄层电阻分析：迁移率与薄层载体浓度。

层间不掺杂和层间掺杂的多层石墨烯都是通过多次铜蚀刻（无掺杂或在蚀刻过程中掺杂）多次转移石墨烯层而制备的，界面性质对多层石墨烯电性能的影响为通过将层数从1更改为12进行调查。在这两种情况下，薄层电阻都随层数的增加而从无夹层石墨烯的700到104Ω/ sq和从夹层从280到25Ω/ sq减小掺杂的石墨烯。此外，霍尔测量结果表明，在两种情况下，薄层电阻减小的起因是不同的。在没有层间掺杂的石墨烯中，薄层电阻降低是因为随着增加内层，迁移率增加，具有低载流子密度和高载流子迁移率。另一方面，由于层间掺杂的多层石墨烯中片载流子密度的增加而降低。两种情况下的迁移率和载流子密度变化均通过异质结中的霍尔效应模型进行了验证。此外，我们发现通过掺杂顶层和形成具有不同部分覆盖率的双层石墨烯来改变表面性能，可以分别控制载流子密度和迁移率。我们的研究为控制用于电子应用的多层石墨烯的性能提供了一种有效的方法。两种情况下的迁移率和载流子密度变化均通过异质结中的霍尔效应模型进行了验证。此外，我们发现通过掺杂顶层和形成具有不同部分覆盖率的双层石墨烯来改变表面性能可以单独控制载流子密度和迁移率。我们的研究为控制用于电子应用的多层石墨烯的性能提供了一种有效的方法。两种情况下的迁移率和载流子密度变化均通过异质结中的霍尔效应模型进行了验证。此外，我们发现通过掺杂顶层和形成具有不同部分覆盖率的双层石墨烯来改变表面性能，可以分别控制载流子密度和迁移率。我们的研究为控制用于电子应用的多层石墨烯的性能提供了一种有效的方法。

更新日期：2020-07-08

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