Abstract The microstructural characteristics of two polycrystalline silicon (poly-Si) films with different electrical properties produced by low-pressure chemical vapour deposition on top of high resistivity silicon substrates were investigated by advanced transmission electron microscopy (TEM), including high resolution aberration corrected TEM and automated crystallographic orientation mapping in TEM. The results reveal that the nature of the poly-Si film/Si substrate interface is the main factor controlling the electrical resistivity of the poly-Si films. The high resistivity and high electrical linearity of poly-Si films are strongly promoted by the ∑3 twin type character of the poly-Si/Si substrate interface, leading to the generation of a huge amount of extended defects including stacking faults, ∑3 twin boundaries as well as ∑9 grain boundaries at this interface. Furthermore, a high density of interfacial dislocations has been observed at numerous common and more exotic grain boundaries deviating from their standard crystallographic planes. In contrast, poly-Si film/Si substrate interfaces with random character do not favour the formation of such complex patterns of defects, leading to poor electrical resistivity of the poly-Si film. This finding opens windows for the development of high resistivity silicon substrates for Radio Frequency (RF) integrated circuits (ICs) applications.

中文翻译：

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多晶硅膜/衬底界面在高质量射​​频硅衬底中作用的 TEM 研究

摘要 利用先进的透射电子显微镜 (TEM)，包括高分辨率像差校正 TEM，研究了通过低压化学气相沉积在高电阻率硅衬底上产生的两种不同电性能的多晶硅 (poly-Si) 薄膜的微观结构特征。和 TEM 中的自动晶体取向映射。结果表明，多晶硅薄膜/硅衬底界面的性质是控制多晶硅薄膜电阻率的主要因素。多晶硅/硅衬底界面的∑3孪晶型特征强烈促进了多晶硅薄膜的高电阻率和高电线性度，导致大量扩展缺陷的产生，包括堆垛层错，∑3孪晶界以及∑9晶界在该界面。此外，在偏离其标准晶面的许多常见和更奇特的晶界处观察到高密度的界面位错。相反，具有随机特性的多晶硅膜/硅衬底界面不利于形成这种复杂的缺陷图案，导致多晶硅膜的电阻率较差。这一发现为开发用于射频 (RF) 集成电路 (IC) 应用的高电阻率硅衬底打开了窗口。具有随机特性的多晶硅膜/硅衬底界面不利于形成这种复杂的缺陷图案，导致多晶硅膜的电阻率较差。这一发现为开发用于射频 (RF) 集成电路 (IC) 应用的高电阻率硅衬底打开了窗口。具有随机特性的多晶硅膜/硅衬底界面不利于形成这种复杂的缺陷图案，导致多晶硅膜的电阻率较差。这一发现为开发用于射频 (RF) 集成电路 (IC) 应用的高电阻率硅衬底打开了窗口。