扇形晶圆和面板级包装作为异构集成的包装平台。,Micromachines

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扇形晶圆和面板级包装作为异构集成的包装平台。
Micromachines ( IF 3.0 ) Pub Date : 2019-05-28 , DOI: 10.3390/mi10050342
Tanja Braun ₁ , Karl-Friedrich Becker ₁ , Ole Hoelck ₁ , Steve Voges ₁ , Ruben Kahle ₁ , Marc Dreissigacker ₂ , Martin Schneider-Ramelow ₂

Affiliation

扇出晶圆级封装（FOWLP）是微电子领域的最新封装趋势之一。除了向异构集成的技术发展（包括多管芯封装，封装中的无源组件集成和再分布层或封装上封装方法）外，还针对更大的基板格式。目前，制造是在分别达到12“ / 300 mm和330 mm的晶圆水平上进行的。为了提高生产率并因此降低成本，引入了更大的外形尺寸。面板不是遵循晶圆水平路线图到450 mm，而是面板级别封装（PLP）可能是下一步，这两种技术方法都提供了许多机会，例如高度小型化并且非常适合异构集成。FOWLP和PLP非常适合用于高度小型化的能量收集器系统的包装，该系统由基于压电的收集器，电源管理单元和用于存储能量的超级电容器组成。在这项研究中，已选择FOWLP和PLP方法用于具有集成SMD（表面安装器件）电容器的专用集成电路（ASIC）封装开发。工艺发展和成功的封装方法总体概念验证均在200毫米晶圆尺寸上完成。第二步，使用相同的材料，设备和工艺流程，将该技术扩展到457×305 mm2的面板尺寸，证明了该方法的低成本和大面积功能。在这项研究中，已选择FOWLP和PLP方法用于具有集成SMD（表面安装器件）电容器的专用集成电路（ASIC）封装开发。工艺发展和成功的封装方法总体概念验证均在200毫米晶圆尺寸上完成。第二步，使用相同的材料，设备和工艺流程，将该技术扩展到457×305 mm2的面板尺寸，证明了该方法的低成本和大面积功能。在本研究中，已选择FOWLP和PLP方法用于具有集成SMD（表面安装器件）电容器的专用集成电路（ASIC）封装开发。工艺发展和成功的封装方法总体概念验证均在200毫米晶圆尺寸上完成。第二步，使用相同的材料，设备和工艺流程，将该技术扩展到457×305 mm2的面板尺寸，证明了该方法的低成本和大面积功能。

"点击查看英文标题和摘要"

Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration.

Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12"/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm2 panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.

更新日期：2019-11-01

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