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ACM Transactions on Architecture and Code Optimization
基本信息
期刊名称 ACM Transactions on Architecture and Code Optimization
ACM T ARCHIT CODE OP
期刊ISSN 1544-3566
期刊官方网站 http://dl.acm.org/citation.cfm?id=J924
是否OA No
出版商 Association for Computing Machinery (ACM)
出版周期 Quarterly
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始发年份
年文章数 43
影响因子 1.5(2023)  scijournal影响因子  greensci影响因子
中科院SCI期刊分区
大类学科 小类学科 Top 综述
工程技术4区 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 计算机:硬件4区
COMPUTER SCIENCE, THEORY & METHODS 计算机:理论方法4区
CiteScore
CiteScore排名 CiteScore SJR SNIP
学科 排名 百分位 1.94 0.274 1.095
Computer Science
Hardware and Architecture
59 / 152 61%
Computer Science
Information Systems
111 / 269 58%
Computer Science
Software
165 / 360 54%
补充信息
自引率 6.7%
H-index 32
SCI收录状况 Science Citation Index Expanded
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PubMed Central (PMC) http://www.ncbi.nlm.nih.gov/nlmcatalog?term=1544-3566%5BISSN%5D
投稿指南
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The ACM Transactions on Architecture and Code Optimization (TACO) is a Gold Open Access Journal that focuses on hardware, software, and system research spanning the fields of computer architecture and code optimization. Articles that appear in TACO present new techniques and concepts or report on experiences and experiments with actual systems. Insights useful to computer architects, hardware or software developers, system designers and tool builders are emphasized. This journal is published on a quarterly basis.

Among the topics within the scope of TACO are the following:

Computer system architectures and processor architectures, including multiprocessors and multithreaded computers
Interaction of operating systems, compilers, programming languages, and architecture
Feedback-Directed Software/Hardware Optimization
Dynamic compilation, adaptive execution, and continuous profiling/optimization
Virtual machine, binary translation hardware, and software optimizations
Compiler optimizations that exploit instruction level parallelism, such as software pipelining, global scheduling, register allocation, and memory disambiguation
Advanced software and hardware speculation, prediction, and predication techniques
High-performance microarchitecture innovation (e.g., VLIW, superscalar, multithreaded, etc.)
Architectures and compilers for embedded processors, application specific processors and DSPs, including network and router architectures
Memory system optimization
Parallel processing
Architecture or compiler-based power and energy optimization
Application characterization and architectural implications
Performance evaluation and measurement of real systems
Papers of interest to the SIGMICRO, SIGARCH, and SIGPLAN community
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