马昱春 - 清华大学 - 计算机科学与技术系

个人简介

教育背景工学学士 (计算机科学与技术), 西安交通大学, 中国, 1999 工学博士 (计算机科学与技术), 清华大学, 中国, 2004 研究课题国家自然科学基金重点课题: 面向时序设计的布图规划算法研究 (2007-2009) 奖励与荣誉 ASICON 2007: 最佳论文奖 (2007) 研究概况我主要从事集成电路设计自动化领域的基础算法研究工作，在布图规划算法、三维芯片规划设计、面向微处理器性能优化的布图规划设计、以及面向功耗和时延优化的规划设计等方面开展研究，曾于2005年在美国加州大学洛杉矶分校访问一年，从事三维芯片布图规划和微处理器系统布图规划研究，并参与了3D-MEVA系统的开发。近年来，我在布图规划研究方面取得一系列的科研成果，共发表了40余篇论文（SCI检索9篇、EI检索34篇），包括IEEE Trans. on CAD、ACM Trans. on DAES、ACM Journal on ETC等国际一流学术期刊论文以及10余篇发表在设计自动化方向国际一流学术会议上（DAC、ISPD、ICCAD等）的论文。我还获得了International Conference on ASIC 2001的最佳论文奖以及ASPDAC 2010的最佳论文候选。与此同时，我还从事二维和三维芯片的物理设计优化方法研究，将时序设计、物理位置约束以及功耗优化问题集成在自动优化过程中。面向三维芯片布图中多目标、多约束的复杂情况，我们提出了基于力模型的解析式求解方法。此外，我们提出的增量式设计流程以及相关算法，从流程和算法角度帮助复杂设计实现快速的收敛过程。我从事的研究以芯片设计的性能和可靠性为优化目标，横跨计算机算法与电子设计两个学科，具有一定的交叉性。我与国内外大学的多位教授有深入的合作，目的是利用计算机领域的算法，结合电子设计的特点，实现对设计的优化和算法的加速。

研究领域

集成电路设计自动化，算法设计与分析

近期论文

查看导师最新文章（温馨提示：请注意重名现象，建议点开原文通过作者单位确认）

Yuchun Ma, Xin Li, Yu Wang and Xianlong Hong. Thermal-Aware Incremental Floorplanning for 3D ICs based on MILP Formulation. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no.12, pp. 2979-2989, 2009. Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, and Jason Cong. Investigating the Effects of Fine-Grain Three-Dimensional Integration on Microarchitecture Design. ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, Vol.4 (4), No. 17,2008. Yuchun Ma, Xianlong Hong, Sheqin Dong, C.K. Cheng, and Jun Gu. General floorplans with L/T-shaped blocks using corner block list. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, Vol. 21, No.6, pp. 922-926, 2006. Pingqiang Zhou, Yuchun Ma, Zhouyuan Li, Dick Robert P. , Li Shang, Hai Zhou, Xianlong Hong and Qiang Zhou. 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2007), California, U.S., pp.590-597, 2007. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, C.K. Cheng and Jun Gu. Buffer planning as an integral part of floorplanning with consideration of routing congestion. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol.24, No.4, pp.609-621, 2005. Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng and Jun Gu. Corner Block List Representation and its Application with Boundary Constraints. Science in China Series F-Information Sciences Vol.47, No.1, pp.1-19, 2004. Yuchun Ma, Xianlong Hong, Sheqin Dong,Yici Cai, Chung-Kuan Cheng and Jun Gu. Stairway Compaction using Corner Block List and its Applications with Rectilinear Blocks. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol.9. No.2, pp.199-211, 2004. Yuchun Ma, Xianlong Hong, Sheqin Dong,Song Chen,Yici Cai, Chung-Kuan Cheng and Jun Gu. Dynamic Global Buffer Planning Optimization Based on Detail Block Locating and Congestion Analysis, Prof. 40th Design Automation Conference(DAC2003), pp.806-811， USA, 2003. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu. An Integrated Floorplanning with an Efficient Buffer Planning Algorithm. Prof. International Symposium on Physical Design 2003(ISPD2003), pp.136-142, USA, 2003. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, and Jun Gu. Floorplanning with Abutment Constraints Based on Corner Block List. Integration, the VLSI Journal, Vol.31, pp.65-77, Netherlands, 2001. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng and Jun Gu. Floorplanning with Boundary Constraints Using the Corner Block List(CBL) Representation. IEICE Transactions on Fundamental of Electronics, Communications and Computer Science, Vol. E84A, No.11, pp.2697-2704, 2001. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng and Jun Gu. Floorplanning with abutment constraints and L-shaped/T-shaped blocks based on Corner Block List. Proc. 38th Design Automation Conference (DAC2001), pp.770-775, Las Vegas, USA, 2001.