李昌駿 - 台湾清华大学

个人简介

學歷國立清華大學中華民國動力機械工程學系博士 ~ 2006年國立清華大學中華民國動力機械工程學系碩士 ~ 2002年國立中原大學中華民國機械系學士 ~ 2000年經歷國立清華大學專任副教授動力機械工程學系 2017年 ~ 國立中興大學專任副教授機械系 2016年~2017年國立清華大學兼任副教授動力機械工程學系 2016年~2016年中原大學專任副教授機械系 2014年~2016年中原大學專任助理教授機械系 2011年~2014年台積電主任工程師研發部 2007年~2011年榮譽 2018 榮任 Associate Editor for Microelectronic Reliability Journal 2018 國立清華大學工學院新進人員研究獎國立清華大學工學院 2016 105年度優秀青年工程教授獎中國機械工程學會 2016 年輕力學學者獎中華民國力學學會 2015、2016 台北國際發明暨技術交易展發明競賽銅牌獎 2014 國際先進製造研討會 (ICAM 2014) 優秀年輕學者獎行政院國家科學委員會 2014 103年度中原大學研究傑出獎中原大學 2013、2016 102、105年度行政院科技部優秀年輕學者研究計畫獎勵行政院科技部 2012-2014 中原年輕學者中原大學 2013 102年度吳大猷先生紀念獎資深會員 (IEEE Senior Member) 國際電機電子工程師學會教師_李昌駿_最新研究主題軟性電子與可撓顯示面板之力學設計 3D IC 系統整合與力學設計研究奈微電子元件後段製程改善與可靠度研究矽基與發光二極體元件之散熱系統分析與力學設計應變矽工程學薄膜力學先進微系統構裝計算固體力學多域耦合之非線性有限單元分析多尺度之次模組化模擬

研究领域

•計算固體力學 •軟性電子元件力學 •先進微系統封裝技術 •三維晶片系統設計 •元件應變工程學

近期论文

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研討會論文 1.K. N. Chiang*, V. Ramachandran, K. C. Wu, and C. C. Lee, “Reliability Life Assessment of WLCSP Using Different Creep Models,” The 68th IEEE Electronic Components Technology Conference (ECTC 2018), San Diego, CA, USA, May 29-Jun. 1, 2018. 2.C. C. Lee*, “Material Characteristic Effect of Wafer Level Underfill on the Microbump Reliability of Ultra-Thin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests,” International Multi-Conference on Engineering and Technology Innovation 2017 (IMETI2017), Hualien, Taiwan, Oct. 27-31, 2017. 3.C. C. Lee*, J. Y. He, and P. C. Huang, “Redistributed Geometrical Effect of Cu-Filled Stacked Vias on the Thermal-Induced Stress and Warpage of 3D-ICs Embedded Interposer,” International Multi-Conference on Engineering and Technology Innovation 2017 (IMETI2017), Hualien, Taiwan, Oct. 27-31, 2017. 4.C. C. Lee*, J. Y. He, C. P. Hsieh, C. C. Tsai, and J. C. Chuang, “Influence Estimation of Process-Induced Stress on Flexible Electronics Packaging,” 2017 International Microsystems Packaging Assembly and Circuits Technology Conference (the 12th IMPACT Conference), Taipei, Taiwan. Oct. 25-27, 2017. 5.C. C. Lee*, and P. C. Huang, “Layout Design Effect of Transverse Dummy Polys on Stress-Induced Performance of Ge-Based High-k/Metal Gate NMOSFETs,” TACT 2017 International Thin Films Conference, Hualien, Taiwan, Oct. 15-18, 2017. 6.C. C. Lee*, and P. C. Huang, “Resultant Impacts of Stress Gradient CESL and Embedded S/D SiC Stressors on Nano-Scaled Si-Based Strained NMOSFETs,” TACT 2017 International Thin Films Conference, Hualien, Taiwan, Oct. 15-18, 2017. 7.C. C. Lee*, and C. P. Hsieh, “Succeeded Foundation Effect of Stretched Gate Width and Dummy Diffusion Region on Strained Silicon PMOSFETs,” TACT 2017 International Thin Films Conference, Hualien, Taiwan, Oct. 15-18, 2017. 8.T. C. Cheng*, C. C. Lee, C. C. Chiang, and T. H. Chen, “Improved Field Emission Properties of Carboxylated MWCNTs on Flexible Carbon Cloth Substrate,” The 24th Congress of the International Commission for Optics (ICO-24), Tokyo, Japan, Aug. 21-25, 2017. 9.C. C. Lee*, and P. C. Huang, “Lattice Orientation Effect of Local Stressors on the Width Dependence Performance of High-k Metal Gate PMOSFETs,” 15th International Nanotech Symposium & Exhibition (NANO KOREA 2017), Seoul, Jul. 12-14, 2017. 10.C. C. Lee*, P. C. Huang, and C. W. Wang, “The Development of Estimated Methodology for Interfacial Adhesion of Semiconductor Coatings Having an Enormous Mismatch Extent,” 2nd International Conference on Applied Surface Science (ICASS), Dalian, China, Jun. 12-15, 2017. 11.C. C. Lee*, J. Y. He, P. C. Huang, and C. W. Wang, “Interactive Field Effect of Atomic Bonding Force on Nano-Scale Metal Elastic Modulus By Using Atomistic-Continuum Simulation,” 2nd International Conference on Applied Surface Science (ICASS), Dalian, China, Jun. 12-15, 2017. 12.C. C. Lee*, J. Y. He, P. C. Huang, and H. C. Liu, “Experimental Measurements and Simulated Estimations for the Interfacial Adhesion Between Glass Interposer and SiNx Coatings,” 2nd International Conference on Applied Surface Science (ICASS), Dalian, China, Jun. 12-15, 2017. 13.C. C. Lee*, J. Y. He, P. C. Huang, and H. C. Liu, “Layout Designs of Surface Barrier Coatings for Boosting the Capability of Oxygen/Vapour Obstruction Utilized in Flexible Electronics,” 2nd International Conference on Applied Surface Science (ICASS), Dalian, China, Jun. 12-15, 2017. 14.M. H. Hsu, C. C. Lee, and K. N. Chiang*, “A Modified Acceleration Factor Empirical Equation for BGA Type Package,” The 67th IEEE Electronic Components Technology Conference (ECTC 2017), Orlando, Florida, USA, May 30-Jun. 2, 2017. 15.C. C. Lee*, D. Y. Lee, C. P. Hsieh, and C. H. Liu, “The Effect of Contact-Etch-Stop-Layer and Si1-xGex Channel Mechanical Properties on Nano-Scaled Short Channel NMOSFETs with Dummy Gate Arrays,” 2016 International Electron Devices and Materials Symposium (IEDMS), Taipei, Taiwan, Nov. 24-25, 2016. 16.C. C. Lee*, and P. C. Huang, “Investigation of Chip-Interposer Interaction by Loading the Residual Stress of Copper-Filled Through Silicon Via,” 2016 International Electron Devices and Materials Symposium (IEDMS), Taipei, Taiwan, Nov. 24-25, 2016. 17.J. S. Hsu, C. C. Lee*, B. J. Wen, P. C. Huang, and C. K. Xie, “Experimental and Simulated Investigations of a Thin Polymer Substrate with ITO Coatings under Fatigue Bending Loadings,” International Multi-Conference on Engineering and Technology Innovation 2016 (IMETI2016), Taichung, Taiwan, Oct. 28-Nov. 1, 2016. 18.C. P. Wang*, and C. C. Lee, “Effects of Current Crowding and Temperature Distribution on the Performance of Power LEDs,” International Multi-Conference on Engineering and Technology Innovation 2016 (IMETI2016), Taichung, Taiwan, Oct. 28-Nov. 1, 2016. 19.C. C. Lee*, C. H. Chen, and P. C. Huang “Residual Stress Investigation of TSVs on MOSFETs by Using Submodeling Finite Element Technique,” IEEE International Microsystem, Packaging, Assembly and Circuits Technology Conference (IMPACT-IAAC 2016 Joint Conference), Taipei, Taiwan, Oct. 26-28, 2016. 20.C. C. Lee*, “Stress-Induced Failure Estimation of Embedded Carrier Utilized in 3D-ICs Integrations,” 2nd International Conference on Computing and Precision Engineering (ICCPE), Kenting, Taiwan, Sep. 30-Oct. 3, 2016. 21.C. C. Lee*, “Factorial Designs of Multi-Coatings for Induced Stresses of Advanced Flexible Displays,” 23rd International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD’16), pp. 67-68, Kyoto, Japan, Jul. 6-8, 2016. 22.C. C. Lee*, T. C. Cheng, and P. C. Huang, “Comprehensive Effects of Strained Ge1-xSnx and Device Layout Arrangement on a Nano-Scaled Ge-based PMOSFET with a Short Channel,” International SiGe Technology and Device Meeting (ISTDM 2016), pp. 65-66, Nagoya, Japan, Jun. 7-11, 2016. 23.C. C. Lee*, P. C. Huang, Y. T. Kuo, D. Y. Li, and C. H. Liu, “Interaction Influence of S/D GeSi Lattice Mismatch and Stress Gradient of CESL on Nano-Scaled Strained NMOSFETs,” 7th International Symposium on Control of Semiconductor Interfaces (ISCSI-VII), pp. 43-44, Nagoya, Japan, Jun. 7-11, 2016. 24.C. C. Lee*, P. C. Huang, and B. T. Chian, “Development and Demonstration of Equivalent Material Characteristics for Microbump Arrays Utilized in Failure Estimation of Chip-on-Chip Packaging,” 2016 Intersociety Conference on Thermal and Thermomechanical phenomena in Electronic Systems (ITHERM 2016), Las Vegas, NV, USA, May 31-Jun. 3, 2016. 25.C. C. Lee*, C. P. Hsieh, M. H. Liao, “Accompanied Arrangement Effect of Stretched Gate Width and Dummy Diffusion Region on Strained Silicon PMOSFETs,” 7th IEEE International Nanoelectronics Conference (IEEE INEC2016), Chengdu, China, May 9-11, 2016. 26.H. W. Hsu, and C. C. Lee*, “Device Layout Effect of Strained Ge-Based NMOSFETs with Ge1-xSix Stressors,” 7th IEEE International Nanoelectronics Conference (IEEE INEC2016), Chengdu, China, May 9-11, 2016. 27.C. C. Lee*, Y. H. Guo, H. C. Liu, Y. M. Lin, and T. C. Chang, “Managing Induced Warpage of 3D-ICs Packaging Using Multi-Layered Molding Materials,” 7th IEEE International Nanoelectronics Conference (IEEE INEC2016), Chengdu, China, May 9-11, 2016. 28.Y. T. Kuo, D.Y. Li, C. C. Lee, and C. H. Liu*, “Stress Gradient Influence of Tensile Contact Etch Stop Layer on Strained NMOSFETs,” 2015 International Electron Devices and Materials Symposium (IEDMS), Tainan, Taiwan, Nov. 19-20, 2015. 29.C. C. Lee*, S. W. Cheng, and Y. Y. Liou, “Adhesion Investigation of Stacked Thin Film in Organic Light-Emitting Diode Display Architecture,” TACT 2015 International Thin Films Conference, Tainan, Taiwan, Nov.15-18, 2015. 30.C. C. Lee*, S. W. Cheng, and P. C. Huang, “STI Geometrical Influence of Recessed Surface on Array-Type Arrangements of Nano-Scaled Devices Strained by CESL and Ge-based Stressors,” TACT 2015 International Thin Films Conference, Tainan, Taiwan, Nov.15-18, 2015. (榮獲TACT2015 國際研討會論文海報競賽佳作) 31.C. C. Lee*, T. L. Tzeng, and P. C. Huang, “Development for Equivalent Material Properties of Microbump Utilized in Simulation of Chip Stacking Packaging,” International Multi-Conference on Engineering and Technology Innovation 2015 (IMETI2015), Kaohsiung, Taiwan, Oct. 30-Nov. 3, 2015. 32.C. H. Chen and C. C. Lee*, “Residual Stress Effect of Copper-Filled Through Silicon Via on Performances of Nano-Scaled Devices in 3D-ICs Interposer,” IEEE International Microsystem, Packaging, Assembly and Circuits Technology Conference (the 10th IMPACT Conference), Taipei, Taiwan, Oct. 21-23, 2015. (榮獲IEEE IMPACT 2015 國際研討會優秀學生論文獎) 33.B. J. Wen, C. C. Lee*, and C. P. Hsieh, “Nano-Structure Fabrication on the Nitride Films by Automatic Scanning Probe Oxidation,” 12th International Symposium on Measurement Technology and Intelligent Instruments (ISMTII 2015), Taipei, Taiwan, Sep. 22-25, 2015. 34.C. C. Lee*, R. C. Cheng, Y. M. Lin, H. N. Liu, Y. Y. Liou, and T. C. Chang, “Solution of Warpage Improvement for Embedded Interposer Carrier Integrated into 3D-ICs Packaging,” International Interconnect Technology Conference/ Materials for Advanced Metallization Conference (IITC/MAM 2015), Grenoble, France, May 18-21, 2015. 35.C. C. Lee*, Y. M. Lin, Y. Y. Liou, C. J. Zhan, and T. C. Chang, “Fabrication, Assembly, Failure Estimations of for Ultra-Thin Chips Stacking by Using Pre-Molding Technology,” International Interconnect Technology Conference/ Materials for Advanced Metallization Conference (IITC/MAM 2015), Grenoble, France, May 18-21, 2015. 36.C. C. Lee*, C. P. Hsieh, S. W. Cheng, and M. H. Liao, “Architecture Investigation of GeSn Alloy and CESL on Strained Ge-Based PMOSFETs,” 9th International Conference on Silicon Epitaxy and Heterostructures (ICSI-9), Montreal, Canada, May 17-22, 2015. 37.C. C. Lee*, C. P. Hsieh, P. C. Huang, S. W. Cheng, and M. H. Liao, “A Performance Study of Ge1-xSix on Ge-Based NMOSFETs by Using Device Simulation Combined with Higher Order Stress-Piezoresistive Relationships,” 9th International Conference on Silicon Epitaxy and Heterostructures (ICSI-9), Montreal, Canada, May 17-22, 2015. 38.C. C. Lee*, T. L. Tzeng, and P. C. Huang, “Development of Simulation-Approach for 3D Chip Stacking with Fine-Pitch Array-Type Microbumps,” 2015 International Conference on Electronics Packaging & iMAPS All Asia Conference (ICEP-IAAC 2015), Kyoto, Japan, Apr. 14-17, 2015. SCI期刊論文 1.C. C. Lee*, and P. C. Huang, “Mixed Mode Interfacial Crack Energy Estimation of Glass Interposer and SiNx Coatings by Using Fracture Mechanics Based Computer Methods and Experimental Validations,” Theoretical and Applied Fracture Mechanics, Vol. 96, pp. 790-794, Aug. 2018. 2.C. C. Lee*, and P. C. Huang, “Material Lattice Orientation Effect of Local Si1-xGex Stressors on the Width Dependence of High-k Metal Gate PMOSFETs,” Current Applied Physics, Vol. 18, pp. S2-S7, Aug. 2018. 3.C. C. Lee*, and P. C. Huang, “The Development of Estimated Methodology for Interfacial Adhesion of Semiconductor Coatings Having an Enormous Mismatch Extent,” Applied Surface Science, Vol. 440, pp. 202-208, May 2018. 4.C. C. Lee*, C. H. Liu*, D. Y. Li, and C. P. Hsieh, “Effect of Contact-Etch-Stop-Layer and Si1-xGex Channel Mechanical Properties on Nano-Scaled Short Channel NMOSFETs with Dummy Gate Arrays,” Microelectronics Reliability, Vol. 83, pp. 230-234, Apr. 2018. 5.C. C. Lee*, P. C. Huang, and J. Y. He “Layout Designs of Surface Barrier Coatings for Boosting the Capability of Oxygen/Vapor Obstruction Utilized in Flexible Electronics,” Applied Surface Science, Vol. 436, pp. 183-188, Apr. 2018. 6.H. W. Hsu, and C. C. Lee*, “Effect of Strained Ge-Based NMOSFETs with Ge0.93Si0.07 Stressors on Device Layout,” Solid-State Electronics, Vol. 138, pp. 113-118, Dec. 2017. 7.C. C. Lee*, Y. T. Kuo, and C. H. Liu*, “Interaction Influence of S/D GeSi Lattice Mismatch and Stress Gradient of CESL on Nano-Scaled Strained NMOSFETs,” Materials Science in Semiconductor Processing, Vol. 70, pp. 254-259, Nov. 2017. 8.C. C. Lee* and P. C. Huang, “Comprehensive Effects of Strained Ge1-xSnx and Device Layout Arrangement on a Nano-scale Ge-based PMOSFET with a Short Channel,” Materials Science in Semiconductor Processing, Vol. 70, pp. 145-150, Nov. 2017. 9.C. C. Lee*, “Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests,” Materials, Vol. 10, No. 10, pp. 1220, Oct. 2017. 10.M. H. Liao*, H. Y. Huang, F. A. Tsai, C. C. Chuang, M. H. Hsu, C. C. Lee, M. H. Lee, C. Lien, C. F. Hsieh, T. C. Wu, H. S. Wu, and C. W. Yao, “The Achievement of the Super Short Channel Control in the Magnetic Ge n-FinFETs with the Negative Capacitance Effect,” Vacuum, Vol. 140, pp. 63-65, Jun. 2017. 11.C. C. Lee*, H. W. Hsu, and M. H. Liao*, “The Effect of CESL and Dummy Poly Gate for n-Type MOSFETs with Short Si0.75Ge0.25 Channel,” Vacuum, Vol. 140, pp. 66-70, Jun. 2017. 12.M. H. Liao*, C. P. Hsieh, and C. C. Lee*, “The Investigation of Self-Heating Effect on Si1-xGex FinFETs with Different Device Structures, Ge Concentration, and Operated Voltages,” AIP Advances, Vol. 7, No. 5, pp. 055105, May 2017. 13.C. K. Yang, T. C. Cheng*, C. H. Cheng*, C. C. Wang, and C. C. Lee, “Open-Loop Altitude-Azimuth Concentrated Solar Tracking System for Solar-Thermal Applications,” Solar Energy, Vol. 147, pp. 52-60, May 2017. 14.M. H. Liao*, C. P. Hsieh, and C. C. Lee*, “The Systematic Investigation of Self-Heating Effect on CMOS Logic Transistors From 20 nm to 5 nm Technology Nodes by Experimental Thermo-Electric Measurements and Finite Element Modeling,” IEEE Transactions on Electron Devices, Vol. 64, No. 2, pp. 646-648, Feb. 2017. 15.C. C. Lee*, W. C. Wang, P. C. Huang, Y. Y. Liou, and H. N. Liu, “Improvements of Stress Migration in Nano-Scaled Copper Interconnects,” Science of Advanced Materials, Vol. 9, No. 1, pp. 11-16, Jan. 2017. 16.C. C. Lee*, and P. C. Huang, “Stress-induced Failure Predictions of Flexible Electronics with Nano-Scaled Thin-Films,” Science of Advanced Materials, Vol. 9, No. 1, pp. 6-10, Jan. 2017. 17.B. J. Wen, C. C. Lee*, M. W. Chang, H. K. Lin, Y. Y. Liou, and S. W. Cheng, “Surface Properties of Nano-film Type Patterning Electrode on Flexible Substrate for Bending Test,” Science of Advanced Materials, Vol. 9, No. 1, pp. 17-21, Jan. 2017. 18.C. P. Hsieh, M. H. Liao*, C. C. Lee*, T. C. Cheng, C. P. Wang, P. C. Huang, and S. W. Cheng “Shallow Trench Isolation Geometric Influence of a Recessed Surface on Array-type Arrangements of Nano-scaled Devices Strained by Contact Etch Stop Liner and Ge-based Stressors,” Thin Solid Films, Vol. 618, Part A, pp. 172-177, Nov. 2016. 19.C. C. Lee*, P. C. Huang, and K. S. Wang, “Flexural Capability of Patterned Transparent Conductive Substrate by Performing Electrical Measurements and Stress Simulations,” Materials, Vol. 9, No. 10, pp. 850, Oct. 2016. 20.C. C. Lee*, C. C. Tsai, J. C. Chuang, P. C. Huang, S. W. Cheng, and Y. Y. Liou, “Adhesion Investigation of Stacked Coatings in Organic Light-Emitting Diode Display Architecture,” Surface and Coatings Technology, Vol. 303, pp. 226-231, Oct. 2016. 21.C. C. Lee*, S. W. Cheng, C. P. Hsieh, M. H. Liao, and Y. H. Guo, “Comprehensive Investigation on Array-Type Dummy Active Diffused Region and Gate Geometries Using Narrow NMOSFETs with SiC S/D Stressors,” International Journal of Nanotechnology, Vol. 13, No. 7, pp. 492-508, 2016. 22.J. S. Hsu, C. C. Lee*, B. J. Wen, P. C. Huang, and C. K. Xie, “Experimental and Simulated Investigations of Thin Polymer Substrates with an Indium Tin Oxide Coating under Fatigue Bending Loadings,” Materials, Vol. 9, No. 9, pp. 720, Aug. 2016. 23.C. C. Lee, R. C. Cheng, Y. M. Lin, H. N. Liu, Y. Y. Liou, T. C. Chang, C. P. Wang*, “Flatness Enhancement of the Embedded Interposer of 3D-ICs by Using Ring-Type Framework Designs,” Microelectronic Engineering, Vol. 156, pp. 30-36, Apr. 2016. 24.C. C. Lee, Y. M. Lin, C. P. Hsieh, Y. Y. Liou, C. J. Zhan, T. C. Chang, C. P. Wang*, “Assembly Technology Development and Failure Analysis for Three-Dimensional Integrated Circuit Integration with Ultra-Thin Chips Stacking,” Microelectronic Engineering, Vol. 156, pp. 24-29, Apr. 2016. 25.M. H. Liao*, C. H. Yeh, C. C. Lee, and C. P. Wang, “The Investigation of the Diameter Dimension Effect on the Si Nano-Tube Transistors,” AIP Advances, Vol. 6, No. 3, pp. 035021, Mar. 2016. 26.C. C. Lee*, C. P. Hsieh, P. C. Huang, S. W. Cheng, and M. H. Liao, “Ge1-xSix on Ge-Based N-Type Metal-Oxide Semiconductor Field-Effect Transistors by Device Simulation Combined with High-Order Stress–Piezoresistive Relationships,” Thin Solid Films, Vol. 602, pp. 78-83, Mar. 2016. 27.T. C. Chang, C. C. Lee*, C. P. Hsieh, S. C. Hung, and R. S. Cheng, “Electrical Characteristics and Reliability Performance of IGBT Power Device Packaging by Chip Embedding Technology,” Microelectronics Reliability, Vol. 55, No. 12, pp. 2582-2588, Dec. 2015. 28.C. C. Lee*, S. T. Chang, S. W. Cheng, and B. T. Chian, “Performance Investigation of Nanoscale Strained Ge pMOSFETs with a GeSn Alloy Stressor,” Journal of Nanoscience and Nanotechnology, Vol. 15, No. 11, pp. 9158-9162, Nov. 2015. 29.C. C. Lee*, and C. C. Huang, “Induced Thermo-Mechanical Reliability of Copper-Filled TSV Interposer by Transient Selective Annealing Technology,” Microelectronics Reliability, Vol. 55, No. 11, pp. 2213-2219, Nov. 2015. 30.C. C. Lee*, Y. L. Shen, and Y. Kang, “Prediction of Interfacial Adhesion Strength of Nanoscale Al/TiN Films Passed Through Patterned BEOL Interconnects,” Materials Science in Semiconductor Processing, Vol. 39, pp. 1-5, Nov. 2015. 31.B. J. Wen, C. C. Lee*, J. S. Hsu, P. C. Huang, and C. H. Tsai, “Investigation of Optical and Flexible Characteristics for Organic-Based Cholesteric Liquid Crystal Display by Utilizing Bending and Torsion Loadings,” IEEE/OSA Journal of Display Technology, Vol. 11, No. 9, pp. 682-688, Sep. 2015. 32.J. Y. Chang, S. Y. Huang, C. C. Lee, T. H. Chuang, and T. C. Chang*, “Influence of Glass Transition Temperature of Underfill on the Stress Behavior and Reliability of Microjoints Within a Chip Stacking Architecture,” Journal of Electronic Packaging, Vol. 137, No. 3, pp. 031007, Sep. 2015. 33.C. C. Lee*, T. L. Tzeng, and P. C. Huang, “Development of Equivalent Material Properties of Microbump for Simulating Chip Stacking Packaging,” Materials, Vol. 8, No. 8, pp. 5121-5137, Aug. 2015. 34.C. C. Lee*, Y. M. Lin, Y. H. Guo, C. J. Zhan, T. C. Chang, and Y. H. Dzeng, “Assembly Reliability Improvement of 3D-ICs Packaging Using Pre-Stuffed Molding Material,” Vacuum, Vol. 118, pp. 152-160, Aug. 2015. 35.C. C. Lee*, P. J. Wei, B. T. Chian, C. H. Tsai, and Y. H. Dzeng, “Predictions and Measurements of Interfacial Adhesion among Encapsulated Thin Films of Flexible Devices,” Thin Solid Films, Vol. 584, pp. 154-160, Jun. 2015. 36.C. C. Lee*, C. H. Liu, H. C. Cheng, and R. H. Deng, “Structural Optimizations of Silicon Based NMOSFETs with a Sunken STI Pattern by Using a Robust Stress Simulation Methodology,” Journal of Nanoscience and Nanotechnology, Vol. 15, No. 3, pp. 2179-2184, Mar. 2015. 37.C. C. Lee*, C. H. Liu, Z. H. Chen, and T. L. Tzeng, “A Resultant Stress Effect of Contact Etching Stop Layer and Geometrical Designs of Poly Gate on NanoScaled nMOSFETs with a Si1-xGex Channel,” Journal of Nanoscience and Nanotechnology, Vol. 15, No. 3, pp. 2173-2178, Mar. 2015. 技術報告與專書 1.李昌駿, 林耀生, 2003, “ COG 專利搜尋報告(COG Patent Survey Report ),” 工業技術研究院技術報告, October. (In Chinese) 2.許永昱, 張恕銘, 李昌駿, 江國寧, 2004, “微液相成形混合理論應用於晶圓級封裝可靠性與微結構體自動組裝研究,” 工業技術研究院技術報告, July. (In Chinese) 3.李昌駿, 2011, “矽基LED 微機電封裝結構設計與應力分析,” 中國工程師學會“工程”會刊,Vol. 84, No. 3, pp. 44-54, Jun., 2011. (In Chinese) 4.C. C. Lee and K. N. Chiang (2014) Thermal Stress Induced Interfacial Failure Modes of Advanced Electronic Devices. In Hetnarski RB (Ed.) Encyclopedia of Thermal Stresses, Vol 1, pp 5469 – 5495. Springer Dordrecht, Heidelberg, New York, London. 5.李昌駿, 黃北辰, 何婧妍, 2016, “前瞻軟性顯示器之機械力學行為研究,” 機械工業雜誌, Vol. 402, pp. 73-84, Sep., 2016. (In Chinese)