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论文
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1. WenLan Wu, "Monotonic Multi-Switching Method for Ultra-Low-Voltage Energy Efficient SAR ADCs", , , Jun-2013
期刊和杂志
共计: 33
33. Wei Wang, Chi Hang Chan, Yan Zhu, R. P. Martins, "A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization", IEEE Journal of Solid-State Circuits, Jun-2020.
32. Wenning Jiang, Yan Zhu, Chi Hang Chan, R. P. Martins, "A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier", IEEE Journal of Solid-State Circuits, Feb-2020.
31. Yan Song, Chi Hang Chan, Yan Zhu, R. P. Martins, "A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC", IEEE Journal of Solid-State Circuits, Feb-2020.
30. Xuewei Lei, Yan Zhu, Chi Hang Chan, R. P. Martins, "A 4-b 7µW Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation", IEEE Transactions on Circuits and Systems I: Regular Papers, Sep-2019.
29. Cheng Li, Chi Hang Chan, Yan Zhu, R. P. Martins, "Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC", IEEE Transactions on Circuits and Systems I: Regular Papers, Jan-2019.
28. Yan Zhu, Chi Hang Chan, Zi Hao Zheng, Cheng Li, Jianyu Zhong, R. P. Martins, "A 0.19 mm² 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS", IEEE Transactions on Circuits and Systems I: Regular Papers,, Nov-2018.
27. Wang GuanCheng, Cheng Li, Yan Zhu, Jianyu Zhong, Yan Lu, Chi Hang Chan, R. P. Martins, "Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC", IEEE Transactions on Circuits and Systems I: Regular Papers, Nov-2018.
26. Wang GuanCheng, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Nov-2018.
25. Wei Wang, Yan Zhu, Chi Hang Chan, R. P. Martins, "A 5.35-mW 10-MHz Single-Opamp Third-Order CTΔΣModulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS", IEEE Journal of Solid-State Circuits, Oct-2018.
24. Yang Xiaofeng, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology", IEEE Transactions on Circuits and Systems I: Regular Papers, Jun-2018.
23. Chi Hang Chan, Yan Zhu, Zhang WaiHong, Seng-Pan U, R. P. Martins, "A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC with Background Offset Calibration", IEEE Journal of Solid-State Circuits, Mar-2018.
22. Yan Song, Chi Hang Chan, Yan Zhu, Li Geng, Seng-Pan U, R. P. Martins, "Passive Noise Shaping in SAR ADC With Improved Efficiency", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb-2018.
21. Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek, Yan Zhu, Seng-Pan U, "A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Dec-2017.
20. Chi Hang Chan, Yan Zhu, Cheng Li, Zhang WaiHong, Ho Iok Meng, Lai Wei, Seng-Pan U, R. P. Martins, "60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration", IEEE Journal of Solid-State Circuits, Oct-2017.
19. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 7.8mW 5b 5GS/s Dual-Edges-Triggered Time-Based Flash ADC", in IEEE Transactions on Circuits and Systems I: Regular paper, Aug-2017.
18. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC", IEEE Transactions on Circuits and Systems I: Regular paper, Jul-2017.
17. Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, "Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Mar-2017.
16. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Boris Murmann, Seng-Pan U, R. P. Martins, "Metastablility in SAR ADCs", press in IEEE Transactions on CAS – Part II: Express Briefs, Feb-2017.
15. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jan-2017.
14. Yan Lu, Cheng Li, Yan Zhu, Mo Huang, Seng-Pan U, R. P. Martins, "A 312 ps Response-Time LDO with Enhanced Super Source Follower in 28 nm CMOS", Electronics Letters, Aug-2016.
13. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "An 11b 450 MS/s 3-way Time-Interleaved Sub-ranging Pipelined-SAR ADC in 65nm CMOS", IEEE Journal of Solid-State Circuits, May-2016.
12. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC", IEEE Journal of Solid-State Circuits, Feb-2016.
11. Jianwei Lui, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jan-2016.
10. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs", IEEE Transactions on Circuits and Systems I: Regular Papers, Sep-2015.
9. Yan Zhu, Chi Hang Chan, Wong, S.-S., Seng-Pan U, R. P. Martins, "Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Jun-2015.
8. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Split-SAR ADCs: Improved Linearity with Power and Speed Optimization", ", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb-2014.
7. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS", IEEE Journal of Solid-State Circuits, Sep-2013.
6. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC", IEEE Journal of Solid-State Circuits, Aug-2013.
5. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 50fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation", IEEE Journal of Solid-State Circuits, Dec-2012.
4. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC", IEEE Transactions on CAS – Part II: Express Briefs, Aug-2010.
3. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS", IEEE Journal of Solid-State Circuits, Jun-2010.
2. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Linearity Analysis On A Series-Split Capacitor Array for High-Speed SAR ADCs", Hindawi VLSI Design, Special Issue with "Selected Papers from the Midwest Symposium on Circuits and Systems, Apr-2010.
1. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Rapid Power-Switchable Track-and-Hold Amplifier in 90nm CMOS", IEEE Trans. on Circuits and System II – Express Briefs, Jan-2010.
会议报告和简报
共计: 45
45. Kai Xing, Lei Wang, Yan Zhu, Chi Hang Chan, R. P. Martins, "A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SABELD-Merged Integrator and 3-Stage Opamp", 2020 Symposia on VLSI Technology and Circuits, , Jun-2020.
44. Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi Hang Chan, Jan Craninckx, R. P. Martins, "A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation", IEEE International Solid-State Circuits Conference (ISSCC), pp. 254-256, Feb-2020.
43. Yan Song, Yan Zhu, Chi Hang Chan, R. P. Martins, "A 2.56mW 40MHz-Bandwidth 75dB-SNDR PartialInterleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration", IEEE International Solid-State Circuits Conference (ISSCC), pp.164-166, Feb-2020.
42. Minglei Zhang, Yan Zhu, Chi Hang Chan, R. P. Martins, "A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input", IEEE International Solid-State Circuits Conference (ISSCC), pp. 252-254, Feb-2020.
41. Yan Song, Yan Zhu, Chi Hang Chan, R. P. Martins, "9.6 A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial-Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration", 2020 IEEE International Solid- State Circuits Conference - (ISSCC), pp. 164-166, Feb-2020.
40. Minglei Zhang, Yan Zhu, Chi Hang Chan, R. P. Martins, "16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input", 2020 IEEE International Solid- State Circuits Conference - (ISSCC), pp. 252-254., Feb-2020.
39. Wenning Jiang, Yan Zhu, Minglei Zhang, Chi Hang Chan, R. P. Martins, "A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier", IEEE International Solid-State Circuits Conference (ISSCC 2019, pp.60-62, Feb-2019.
38. Minglei Zhang, Chi Hang Chan, Yan Zhu, R. P. Martins, "A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques", IEEE International Solid-State Circuits Conference (ISSCC 2019), pp.66-68, Feb-2019.
37. Wei Wang, Chi Hang Chan, Yan Zhu, R. P. Martins, "A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ", IEEE International Solid-State Circuits Conference (ISSCC 2019), , Feb-2019.
36. Wenning Jiang, Yan Zhu, Chi Hang Chan, Boris Murmann, Seng-Pan U, R. P. Martins, "A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler", 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), [Highlighted Paper], Nov-2018.
35. Chi Hang Chan, Yan Zhu, Zihao Zheng, R. P. Martins, "A 39mW 7b 8GS/s 8-way TI ADC with Cross-linearized Input and Bootstrapped Sampling Buffer Front-end", ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), , Sep-2018.
34. Yan Song, Yan Zhu, Chi Hang Chan, Li Geng, R. P. Martins, "A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure", Proc. IEEE Symposium on VLSI Circuits - VLSI 2018, , Jun-2018.
33. Chi Hang Chan, Yan Zhu, Seng-Pan U, R. P. Martins, "A 7.8mW 5b 5GS/s Dual-Edges-Triggered Time-Based Flash ADC", forthcoming Proc. IEEE International Symposium on Circuits and Systems – ISCAS 2018, , May-2018.
32. Yang Xiaofeng, Yan Zhu, Chi Hang Chan, Wang GuanCheng, Seng-Pan U, "A 430frms 2.4GHz Ring-Oscillator PLL with Backend Discrete-Time Phase Noise Cancellation Achieving 240.5dB Jitter-FoM", IEEE International Solid-State Circuits Conference (ISSCC 2018), [Student Research Preview], Feb-2018.
31. Wei Wang, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A 5.35 mW 10 MHz Bandwidth CT Third-Order ∆∑ Modulator with Single Opamp Achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS", IEEE Asian Solid-State Circuits Conference (A-SSCC), (highlighted paper and suggested to JSSC special issue), pp.285-288, Nov-2017.
30. Wang GuanCheng, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC", ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, Leuven, pp. 239-242., Sep-2017.
29. Chi Hang Chan, Yan Zhu, Ho Iok Meng, Zhang WaiHong, Seng-Pan U, R. P. Martins, "A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset Calibration", IEEE International Solid-State Circuits Conference (ISSCC), pp. 282-284, Feb-2017.
28. Chi Hang Chan, Yan Zhu, Ho Iok Meng, Zhang WaiHong, Chon-Lam Lio, Seng-Pan U, R. P. Martins, "A 0.011mm2 60dB SNDR 100MS/s Reference Error Calibrated SAR ADC with 3pF Decoupling Capacitance for Reference Voltages", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 145-148 (highlighted paper and invited to JSSC special issue), Nov-2016.
27. Lei Qiu, Kai Tang, Yan Zhu, Liter Siek, Yuanjin Zheng, Seng-Pan U, "A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp: 77 – 80, Nov-2016.
26. Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, "Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching", IEEE ISCAS 2017, accepted, Oct-2016.
25. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 Pipelined-SAR ADC with Merged-residue DAC for Noise Reduction", IEEE European Solid-State Circuits Conference – ESSCIRC 2016, pp. 169-172, Sep-2016.
24. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 Full-Calibration Integrated Pipelined-SAR ADC", International Solid State Circuits Conference (ISSCC), Student Research Previews, Feb-2015.
23. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS", Solid- State Circuits Conference - (ISSCC), (Pre-doctoral achievement awards),pp1-3, Feb-2015.
22. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "An 11b 900 MS/s Time-Interleaved Sub-ranging Pipelined-SAR ADC", IEEE European Solid-State Circuit Conference – (ESSCIRC), pp.211-214, Sep-2014.
21. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A 10.4-ENOB 120MS/s SAR ADC with DAC Linearity Calibration in 90nm CMOS", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp 69-72, Nov-2013.
20. WenLan Wu, Yan Zhu, U-Fat Chio, Li Ding, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 0.6V 8B 100MS/s SAR ADC with Minimized DAC Capacitance and Switching Energy in 65nm CMOS", IEEE International Symposium on Circuits and Systems (ISCAS), pp 2239-2242, May-2013.
19. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Inter-Stage Gain Error Self-Calibration of a 31.5fJ 10b 470MS/s Pipelined-SAR ADC", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp 153-156, Nov-2012.
18. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 2.3mW 10-bit 170MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC", IEEE Custom Integrated Circuits Conference – CICC 2012, pp 1-4, Aug-2012.
17. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC", 2012 Symposium on VLSI Circuits Digest of Technical Papers, pp 90-91, Jun-2012.
16. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure", 2012 Symposium on VLSI Circuits Digest of Technical Papers, pp 86-87, Jun-2012.
15. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation", Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic"), pp. 61-64, Nov-2011.
14. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS", Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic"), pp. 233-236, Nov-2011.
13. Seng-Pan U, Sai Weng Sin, Yan Zhu, U-Fat Chio, He Gong Wei, R. P. Martins, "Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs", Proc. of IEEE International Symposium on Radio-Frequency Integration Technology – RFIT’2011, pp. 173-176, Nov-2011.
12. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Multi-Merged-Switched Redundant Capacitive DACs for 2b/cycle SAR ADC", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
11. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, "An 11b 60MS/S 2.1mW Two-Step Time-Interleaved SAR-ADC with Reused S&H", in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2010, pp. 218-221, Sep-2010.
10. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Parasitics Nonlinearity Cancellation Technique for Split DAC Architecture by Using Capacitive Charge-Pump", IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 889-892, Aug-2010.
9. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Voltage Feedback Charge Compensation Technique for Split DAC Architecture in SAR ADCs", IEEE International Symposium on Circuits and Systems – ISCAS 2010, pp. 607-611, May-2010.
8. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Voltage-Controlled Capacitance Offset Calibration Technique for High Resolution Dynamic Comparator", in Proc. of 2009 International SoC Design Conference (ISOCC), pp. 392-395, Nov-2009.
7. Sai Weng Sin, He Gong Wei, U-Fat Chio, Yan Zhu, Seng-Pan U, R. P. Martins, Franco Maloberti, "On-Chip Small Capacitor Mismatches Measurement Technique using Beta-Multiplier-Biased Ring Oscillator", in Proc. of 2009 IEEE Asian Solid-State Circuit Conference (A-SSCC), pp. 49-52, Nov-2009.
6. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Si-Seng Wong, "Parasitic Calibration by Two-Step Ratio Approaching Techinque for Split Capacitor Array SAR ADCs", in Proc. of 2009 International SoC Design Conference (ISOCC), pp. 333-336, Nov-2009.
5. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Process- and Temperature- Insensitive Current-Controlled Delay Generator for Sampled-Data Systems", in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1192-1195, Dec-2008.
4. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Self-Timing Switch-Driving Register by Precharge-Evaluate Logic for High-Speed SAR ADCs", in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1164-1167, Dec-2008.
3. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Power-Efficient Capacitor Structure for High-Speed Charge Recycling SAR ADCs", in Proceedings of IEEE International Conference on Electronics, Circuits, and Systems - ICECS 2008, pp. 642-645, Sep-2008.
2. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Power Scalable 6-bit 1.2GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier", ", in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 5-8, Aug-2008.
1. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs", in Proceedings of IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2008, pp. 922-925, Aug-2008.