鄢贵海 - 中国科学院计算技术研究所 -

个人简介

2005年本科毕业于北京大学信息科学技术学院，同年进入中国科学院计算技术研究所读研究生，2011年1月获得计算机系统结构工学博士学位。中科院计算所研究员，博士生导师

研究领域

计算机系统结构，领域专用计算加速器，智能芯片体系结构

近期论文

查看导师最新文章（温馨提示：请注意重名现象，建议点开原文通过作者单位确认）

Promoting the Harmony between Sparsity and Regularity: A Relaxed Synchronous Architecture for Convolutional Neural Networks, by Wenyan Lu, Guihai Yan, Jiajun Li, Xiaowei Li, Accepted by IEEE Transactions on Computers. ShuttleNoC: Power-adaptable Communication Infrastructure for Many-core Processors, by Hang Lu; Yisong Chang; Guihai Yan; Ning Lin; Xin Wei; Xiaowei Li Transactions on Computer-Aided Design of Integrated Circuits and Systems ( Early Access ), 12 July 2018. FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks, by Wenyan Lu, Guihai Yan, Jiajun Li, Shijun Gong, Yinhe Han, Xiaowei Li, In proceedings of 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), Austin, USA, 4-8 Feb. 2017 CoreRank: Redeeming "Sick Silicon" by Dynamically Quantifying Core-level Healthy Condition, by Guihai Yan, Faqiang Sun, Huawei Li, Xiaowei Li, IEEE Transactions on Computers, Volume: 65, Issue: 3, pp.716 - 729, March 1 2016 EcoUp: Towards Economical Datacenter Upgrading, by Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li Transactions on Parallel and Distributed Systems, Volume: 27, Issue: 7, pp. 1968-1981, July 1 2016 An Analytical Framework for Estimating Scale-out and Scale-up Power Efficiency of Heterogeneous Manycores, by Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li IEEE Transactions on Computers, Volume: 65, Issue: 2, pp. 367-381, Feb. 1 2016 RISO: Relaxed Network-on-Chip Isolation for Cloud Processors, by Hang Lu, Guihai Yan, Yinhe Han, Binzhang Fu, Xiaowei Li, In the Proceedings of Design Automation Conference (DAC2013), Austin, Texas, USA, June 2-6, 2013. AgileRegulator: A Hybrid Voltage Regulator Scheme Redeeming Dark Silicon for Power Efficiency in a Multicore Architecture, by Guihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li, Minyi Guo, Xiaoyao Liang, In the Proceedings of High-Performance Computer Architecture Symposium 2012 (HPCA2012), New Orleans, Louisiana, pp.287-298, Feb. 25-29, 2012. ReviveNet: A Self-adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation, by Guihai Yan, Yinhe Han, Xiaowei Li, IEEE Transactions on Computers (TC), Vol.60, No.9, pp.1219-1232, Sep. 2011. Leveraging the Core-Level Complementary Effects of PVT Variations to Reduce Timing Emergencies in Multi-Core Processors, by Guihai Yan, Xiaoyao Liang, Yinhe Han, Xiaowei Li, In the Proceedings of the 37th Annual International Symposium on Computer Architecture (ISCA'10), Saint-Malo, France. pp.485-496, Jun. 2010.